Server CPU Physical Design Integration Engineer (Staff)

Job Title

Server CPU Physical Design Integration Engineer (Staff)

Role Summary

Join the Nuvia Data Center CPU team in Cambridge to lead physical design integration for high-frequency, high-performance data-center CPU designs. Collaborate with microarchitecture, RTL, CAD, circuit, block-level physical design and SoC teams to deliver production-ready designs from planning through signoff and silicon validation.

Experience Level

Staff / Senior level. Typical experience guidance: Bachelor's +4 years, Master's +3 years, PhD +2 years, or equivalent practical experience.

Responsibilities

Primary responsibilities span the full CPU physical design flow:

• Own final CPU layout database implementation, integration and verification for high-frequency next-generation CPU designs.
• Drive block partitioning, floorplanning, and pin-placement strategies.
• Integrate IP and coordinate with SoC and third-party IP teams to meet technical and interface requirements.
• Partner with CAD and physical-design teams to develop, refine and automate chip-level flows, validation and analysis.
• Perform timing closure, power planning, clock and power distribution, power/noise analysis, and physical verification.
• Identify and resolve issues during the design cycle and capture learnings for future product cycles.
• Provide technical leadership, mentor engineers, and influence cross-functional methodology (Staff-level responsibility).

Requirements

Must-have skills and experience:

• Deep CPU-specific physical design expertise: synthesis, timing closure, multi-power-domain analysis, structured placement and routing.
• Experience with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.
• Proven ability to optimize CPU designs for power, frequency and area and to analyse signoff results to identify bottlenecks.
• Strong scripting and automation skills (Python, TCL, Perl or similar) to improve productivity and debug efficiency.
• Experience collaborating with EDA vendors to develop or optimize tool capabilities for high-speed CPU cores.
• Strong communication skills and proven ability to work effectively with global, cross-functional distributed teams.

Nice-to-have:

• Hands-on experience with hierarchical physical design methodologies and top-level floorplanning through GDS tapeout.
• Experience with advanced process nodes (7nm and below) and integration of hard IP, memory macros, PLLs, and mixed-signal blocks.
• Familiarity with power-aware implementation techniques: power gating, clock gating, IR drop mitigation, EM analysis and power integrity closure.

Education Requirements

Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Experience guidance provided in posting: Bachelor's +4 years, Master's +3 years, PhD +2 years; equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.