Server CPU Physical Design Engineer — Senior/Staff (Cambridge, UK)

Job Title

Server CPU Physical Design Engineer — Senior/Staff (Cambridge, UK)

Role Summary

Join the Nuvia Data Center CPU team in Cambridge to implement high-performance, power-efficient CPU blocks from RTL/netlist through to GDS. Work across floorplanning, placement, clocking, routing, timing closure, power and signoff in collaboration with architecture, RTL, circuit, CAD, SoC integration, and post-silicon teams.

The position is open at Senior through Staff levels; scope and leadership responsibilities scale with experience.

Experience Level

Senior to Staff level. Typical experience varies by grade; candidates commonly range from early senior engineers (multi-year ASIC/CPU experience) up to experienced technical leaders responsible for large, timing-critical blocks.

Responsibilities

Key responsibilities include implementation ownership and delivery of CPU blocks and improving physical design flows.

• Implement CPU blocks from RTL/netlist to GDS: synthesis, floorplan, placement, CTS, routing, ECOs, and signoff.
• Drive timing closure across multiple modes, corners, and operating conditions.
• Debug and resolve issues in timing, congestion, clocking, routing, IR drop, power integrity, EM, and physical verification.
• Collaborate with architecture, RTL, circuit, CAD, SoC integration, and post-silicon teams to improve PPA and product quality.
• Develop and enhance physical design automation, flows, and methodologies to improve productivity and quality of results.
• Use data-driven analysis to identify implementation bottlenecks and improve convergence.
• For Staff-level roles: provide technical leadership, mentor engineers, define implementation strategies, and lead closure of critical blocks or methodology initiatives.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven experience in digital physical design implementation: synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Strong understanding of static timing analysis and timing-closure methodologies, including trade-offs between timing, power, area, congestion, and routability.
• Hands-on experience with industry-standard EDA tools for synthesis, place & route, STA, power analysis, and physical verification (examples: Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal, or equivalents).
• Ability to debug complex issues across timing, congestion, clocking, routing, power, and verification domains.
• Scripting and automation skills (TCL, Python, Perl, or similar).
• Effective communication and ability to collaborate in a global, cross-functional engineering environment.
• Nice-to-have: CPU core or timing-critical compute block experience; advanced process node experience (7nm and below); low-power and clock-optimization techniques; power integrity/IR drop/EM analysis; methodology and automation development; prior technical leadership or mentoring experience for Staff roles.

Education Requirements

Required: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Qualcomm also considers equivalent practical experience. Indicative experience guidance in the posting linked higher grades to greater experience (examples given: Bachelor's + ~2+ years, Master's + ~1+ year, or PhD-level experience), but equivalent experience that demonstrates the required competencies is acceptable.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.