Serdes PHY Analog Design Engineer
QualcommJob Title
Serdes PHY Analog Design Engineer
Role Summary
Design and deliver high-speed SerDes PHY analog circuits for SoCs, focusing on low-power, high-performance transceivers in advanced process nodes. The role is on the SerDes mixed-signal design team and involves architecture analysis, circuit design, verification, and post-silicon bring-up.
Experience Level
Senior - typically requires experienced analog circuit designers (posting targets candidates with ~8+ years of relevant analog/mixed-signal design and post-silicon bring-up experience).
Responsibilities
Primary responsibilities include end-to-end analog PHY design and integration for high-speed SerDes.
- Design analog building blocks: LDOs, high-speed TX/RX (equalizer, sampler, PI, deserializer), bias and reference circuits.
- Design and analyze PLLs (charge pump, loop filter, VCO/DCO, PFD/TDC, high-speed dividers); model loop dynamics and jitter (RJ & DJ).
- Perform schematic-to-post-layout verification, integration sign-off, and support post-silicon bring-up and debug.
- Collaborate with RTL, DD, PD, DV, SoC verification, and post-silicon teams for PHY integration.
- Lead PHY integration activities for SoC-level deliveries when in lead roles; coordinate with test and validation teams.
Requirements
Must-have technical skills and experience to perform the role.
- Proven analog circuit design experience for high-speed SerDes PHYs (TX/RX, serializer/deserializer).
- Experience with PLL design and jitter analysis for SerDes/frequency synthesis.
- Hands-on experience with SPICE simulators and Cadence Virtuoso (and related layout/verification flows).
- Experience in post-silicon bring-up and debug of analog/mixed-signal IP.
- Scripting skills (Shell, Perl, Python) to automate design and verification tasks.
- Ability to take designs from schematic through layout verification to silicon integration and sign-off.
- Strong communication and collaboration skills to work with global cross-functional teams.
- Nice-to-have: prior PHY lead experience (PHY integration to SoC, interaction with HSIO/ATE/SVE/CE teams); familiarity with peripheral PHY protocols (USB, UFS, PCIe); mixed-signal design background.
Education Requirements
Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. Typical experience expectations tied to degree: Bachelor's + ~4+ years, Master's + ~3+ years, PhD + ~2+ years; equivalent practical experience is acceptable.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
