SerDes IP Design Engineer

Job Title

SerDes IP Design Engineer

Role Summary

Work on digital design and verification within a mixed-signal PHY IP team developing high-speed SerDes interfaces (USB4.0v2, USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, MIPI MPHY up to 40 Gbps). The role spans RTL design, block-level verification, synthesis/STA interaction, and prototype testing.

Experience Level

Mid-level. Requires a minimum of 3 years of industry experience in digital design and verification (see Education Requirements for degree guidance).

Responsibilities

Primary responsibilities include design, verification, and cross-team coordination for SerDes PHY IP development.

• Develop and verify RTL and system-level testbenches for SerDes and PHY IP blocks.
• Write block-level test cases, including constrained directed-random tests.
• Define synthesis constraints and work with backend teams to resolve STA and gate-level simulation issues.
• Work with analog, place-and-route, and customer application teams to debug and resolve integration issues.
• Participate in prototype functional and performance testing on test-chips.
• Provide technical mentorship to junior engineers and coordinate across internal teams and external customers.

Requirements

Must-have technical skills and behaviors.

• Practical experience with Verilog and VCS.
• Familiarity with backend synthesis tools (Design Compiler / PrimeTime or equivalent) and synthesis flows.
• Knowledge of digital design methodologies, DFT insertion, ATE production testing, and synthesis constraints.
• Strong understanding of digital signal processing and data recovery circuits.
• Proven ability to work independently, meet tight deadlines, and solve problems creatively.
• Good communication skills for cross-team and customer interactions.
• Ability to guide junior peers and coordinate with senior engineers.

Nice-to-have:

• Scripting in Shell, Perl, Python, or Tcl.
• RTL coding and modeling of analog blocks; complex system-level testbench development.
• Experience defining clock/reset domain crossing constraints and using CDC/RDC tools.
• Experience enhancing and maintaining multi-protocol SERDES PHY IPs.

Education Requirements

Master of Science in Electrical Engineering (MSEE) preferred; Bachelor of Science in Electrical Engineering (BSEE) acceptable when combined with a minimum of 3 years of relevant industry experience. Degrees in Electrical Engineering or related technical fields are expected; equivalent practical experience will be considered.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.