Job Title
Senior Verification Engineer: UVM/SystemVerilog for ASICs
Role Summary
Develop and scale SystemVerilog/UVM testbenches and verification infrastructure for ASIC projects. Drive regression activities and automation, collaborate with cross-functional teams, and report verification status to stakeholders in a fast-paced startup environment.
Experience Level
Senior β minimum 8 years of ASIC verification experience required.
Responsibilities
The role focuses on building verification infrastructure and driving closure:
- Design, implement, and scale UVM/SystemVerilog testbenches and verification environments.
- Develop, run, and maintain regression suites; triage and debug failures.
- Implement functional coverage, scoreboards, assertions, and verification metrics to measure completeness.
- Develop automation and regression scripts using Perl, Python, or similar scripting languages.
- Collaborate with design, firmware, and validation teams to resolve issues and achieve verification closure.
- Report progress, risks, and verification status to stakeholders; prioritize work to meet customer needs.
Requirements
Must-have skills and experience:
- Minimum 8 years of ASIC verification experience.
- Strong expertise in SystemVerilog and UVM methodologies.
- Proficiency in scripting languages such as Perl and Python for automation.
- Experience developing and maintaining regression environments and achieving verification closure.
- Strong debugging and root-cause analysis skills.
- Effective communication and teamwork in an engineering organization.
Nice-to-have:
- Experience with industry simulators and verification flows (e.g., VCS, Questa) and CI integration.
- Prior work in startup or fast-paced product environments.
Education Requirements
Not specified.
About the Company
Company: CodeGeniusRecruit
Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.

Date Posted: 2026-05-29