Senior Verification Engineer - UVM/SystemVerilog (ASICs)
CodeGeniusRecruitJob Title
Senior Verification Engineer - UVM/SystemVerilog (ASICs)
Role Summary
Senior Verification Engineer responsible for designing, developing, and scaling SystemVerilog/UVM testbenches for ASIC verification. The role sits on a verification team within a California startup and focuses on achieving verification closure through regression, collaboration, and clear progress reporting.
Experience Level
Senior — minimum 8 years of ASIC verification experience as stated in the posting.
Responsibilities
Primary day-to-day responsibilities include building and maintaining verification infrastructure and executing regressions to reach closure.
- Design, develop, and scale SystemVerilog/UVM testbenches for ASIC projects.
- Implement and run regression suites to validate designs and track progress toward verification closure.
- Write and maintain scripts (Perl, Python) to automate verification flows and reporting.
- Collaborate with designers, architects, and other verification engineers to diagnose issues and improve test coverage.
- Report verification status and risks to stakeholders; adapt priorities in a startup environment.
Requirements
Must-have technical skills and experience for immediate contribution.
- Minimum 8 years of ASIC verification experience.
- Expertise in SystemVerilog and UVM methodologies.
- Proficiency in scripting languages such as Perl and Python for automation.
- Experience running and maintaining regression environments and achieving verification closure.
- Ability to work effectively in a fast-paced startup environment and communicate progress to stakeholders.
Education Requirements
Not specified.
About the Company
Company: CodeGeniusRecruit
Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.
