Senior Verification Engineer — UVM/SystemVerilog (ASICs)

Job Title

Senior Verification Engineer — UVM/SystemVerilog (ASICs)

Role Summary

Design, develop, and scale SystemVerilog/UVM testbenches and verification environments for ASIC projects. Work within a small engineering team to drive verification closure, report progress, and ensure product quality in a fast-paced startup setting.

Experience Level

Senior-level. Minimum 8 years of ASIC verification experience expected.

Responsibilities

Primary responsibilities include building verification infrastructure, executing regressions, and collaborating with cross-functional teams.

• Design and implement SystemVerilog and UVM testbenches and verification components.
• Develop scalable verification environments and reusable verification IP.
• Create, run, and maintain regression suites and automated test flows.
• Develop scripts and tools to support verification flows (Perl, Python, or similar).
• Analyze failures, debug RTL and verification issues, and drive closure of verification tasks.
• Communicate verification status and risks to engineering stakeholders.

Requirements

Must-have skills and experience for successful performance in this role.

• Minimum 8 years of ASIC verification experience.
• Strong expertise in SystemVerilog and UVM methodologies.
• Proven experience with ASIC regression strategies and verification closure.
• Proficiency in scripting (Perl, Python, or equivalent) to automate flows and analyze results.
• Ability to work in a small/startup engineering team and report progress to stakeholders.

Education Requirements

Not specified.

About the Company

Company: CodeGeniusRecruit

Recruiting/staffing firm focused on technology and engineering roles, matching candidates with employers for remote, contract, and full-time positions.