Senior Verification Engineer — UVM/SystemVerilog (ASIC)
Towards AIJob Title
Senior Verification Engineer — UVM/SystemVerilog (ASIC)
Role Summary
Develop and scale ASIC verification testbenches using SystemVerilog and UVM. Join an engineering team at a California startup to run regressions, achieve verification closure, and report progress to stakeholders.
Experience Level
Senior level — minimum of 8 years of ASIC verification experience required.
Responsibilities
Primary responsibilities include building and maintaining verification environments and executing regression campaigns.
- Design, develop, and scale UVM/SystemVerilog testbenches for ASIC blocks and subsystems.
- Create, maintain, and run regression suites to exercise designs and measure coverage.
- Debug failures, perform root-cause analysis, and drive issues to verification closure.
- Collaborate with design, validation, and cross-functional teams to meet project goals.
- Report verification status, risks, and progress to engineering leads and stakeholders.
- Automate verification flows and support regression/CI infrastructure as needed.
Requirements
Must-have technical skills and experience.
- Minimum 8 years of ASIC verification experience.
- Expert knowledge of SystemVerilog and UVM methodologies.
- Proficiency in scripting for automation (Perl and Python specified).
- Experience owning regression activities and driving verification to closure.
- Strong debugging and root-cause investigation skills.
- Ability to work effectively in a startup environment and communicate with customers and stakeholders.
Nice-to-have:
- Experience improving verification infrastructure and CI integration.
- Prior mentorship or technical leadership within verification teams.
Education Requirements
Not specified.
About the Company
Company: Towards AI
AI-focused media and technology company that publishes articles, tutorials, and resources for machine learning and artificial intelligence practitioners, and provides community tools and products for AI professionals.
