Senior Verification Engineer - LSU (Load/Store Unit) and Data Cache

Job Title

Senior Verification Engineer - LSU (Load/Store Unit) and Data Cache

Role Summary

Own verification of the Load/Store Unit, data cache and bus interfaces for a CPU/GPU core. The role is responsible for defining and executing the verification plan, collaborating with architecture and design teams, and driving the block to tapeout-quality sign-off.

Position is based in Barcelona with a hybrid schedule (4 days on-site, 1 day remote) and regular cross-team interaction.

Experience Level

Senior - 5+ years in ASIC functional verification, with leadership or mentorship experience preferred.

Responsibilities

Key responsibilities include planning, implementation, and sign-off of LSU and data-cache verification:

• Define and own the LSU verification plan: functional coverage, testplan, checkers, and closure criteria.
• Design and extend UVM/SystemVerilog testbench components (drivers, monitors, scoreboards, memory models).
• Develop directed and constrained-random tests for store-to-load forwarding, memory ordering (RISC-V WMO), speculative loads, vector and misaligned/split accesses, exceptions/faults, and pipeline hazards.
• Use formal techniques for ordering/coherence properties where simulation coverage is insufficient.
• Debug RTL and testbench failures; triage, root-cause, and drive fixes with design teams.
• Track and close functional and code coverage; report verification status to program leads.
• Mentor junior verification engineers and review testbench code and testplans.
• Coordinate with architecture, design, and DV leads on cross-unit interactions and issues.

Requirements

Concise list of must-have and nice-to-have skills and tools.

• Must-have: Hands-on SystemVerilog and UVM experience with testbench architecture and implementation.
• Must-have: Deep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models, and load/store pipelines.
• Must-have: Mandatory knowledge of the RISC-V ISA and privileged specification.
• Must-have: Mandatory experience with AMBA protocols: AXI4, AXI5Lite and CHI.
• Must-have: Experience with coverage-driven verification and regression management.
• Must-have: Proficiency debugging complex RTL failures using waveform tools (e.g., Verdi, DVE).
• Nice-to-have: Formal verification experience (JasperGold or similar) applied to memory ordering/coherence.
• Nice-to-have: Prior verification experience specifically on LSU, cache, or memory-controller blocks.
• Nice-to-have: Familiarity with CPU architecture and memory execution pipeline; experience with RISC-V, ARM, or x86 memory models.
• Nice-to-have: Scripting for verification infrastructure and automation (Python, Perl) and experience with emulation platforms (Veloce, ZeBu) or SystemC/C++ testbenches.
• Soft skills: Adversarial, gap-seeking mindset; clear communication across DV, design, and software teams; ability to write usable verification plans.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (BS/MS in EE/CE/CS as stated in the posting).

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.