Senior Verification Engineer – Core Testbench & DV Methodology Lead

Job Title

Senior Verification Engineer - Core Testbench & DV Methodology Lead

Role Summary

Lead ownership and evolution of the top-level (core) UVM testbench, verification methodology, tooling, and CI infrastructure for a processor core. Drive coverage closure, identify cross-unit verification gaps, and integrate unit-level VIPs to ensure reusable, coverage-driven verification at the core level.

Serve as a technical lead and mentor across the design verification organization and participate in advancing AI-assisted verification methodology initiatives.

Experience Level

Senior / Principal level. Requires substantial engineering leadership with typically 10+ years of hands-on design verification experience.

Responsibilities

Primary responsibilities focus on maintaining and improving the core-level verification environment, ensuring coverage-driven verification, and keeping verification flows current and efficient.

• Own and evolve the top-level core testbench and UVM environment; integrate block-level VIPs and reuse monitors/checkers at core level.
• Drive functional and code coverage closure for the core; review nightly results and audit covergroups and tests for intent and quality.
• Detect and close verification holes at boundaries between units; reconcile assume/guarantee relationships across unit testbenches.
• Maintain and improve verification flows (compile, coverage collection, regression) and CI: update compile configs, retire stale jobs, create efficient regressions.
• Lead migrations and upgrades of scripts/tools and coordinate with EDA vendors to adopt newer simulator and coverage capabilities.
• Provide technical leadership: review testbench architectures, mentor engineers, and promote coverage-driven and assertion-based verification practices.

Requirements

Core technical and hands-on skills required to perform the role. Education details are in the Education Requirements section below.

Must-have

• 10+ years of hands-on design verification experience, including significant experience verifying processor cores or complex microarchitecture.
• Expert-level SystemVerilog and UVM; experience building reusable, configurable multi-agent environments and integration testbenches.
• Strong functional-coverage and verification-planning skills; experience driving coverage closure across multiple teams.
• Deep practical experience with Questa (primary simulator) and a waveform/debug tool (e.g., Visualizer, Verdi); familiarity with other simulators (VCS, Xcelium) is a plus.
• Strong scripting skills in Python and practical experience with Bash/Tcl for automation and CI/CD of verification regressions.
• Experience with assertion-based verification (SVA) and reasoning about cross-block assume/guarantee contracts.
• Proven ability to lead verification flows, maintain regressions, and improve CI efficiency.

Nice-to-have

• Experience with RISC-V core verification.
• Formal verification experience.
• Familiarity with emulation platforms (Veloce, ZeBu) and core/bus protocols (e.g., AXI, CHI).

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.