Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Join NVIDIA's Display Team to verify GPU and SoC display engines used across consumer, professional, automotive, and AI products. You will own verification scope and testplan development, build scalable UVM-based infrastructure, drive verification sign-off, and collaborate with architects, ASIC engineers, external partners, and customers to ensure high-quality silicon.

Experience Level

Senior — requires 10+ years of relevant verification experience.

Responsibilities

Primary responsibilities include planning and executing verification activities, building infrastructure, and collaborating across teams to deliver silicon-ready IP.

• Define verification scope and develop functional and performance testplans.
• Design and implement scalable UVM testbenches, checkers, and constrained-random stimulus.
• Develop and maintain C/C++-based testbenches, debug reference models, and HLS-derived designs.
• Track metrics and drive functional coverage closure to verification sign-off.
• Debug complex integration issues across teams and tool stacks; partner with external partners and customers as needed.
• Collaborate with architects to evaluate and validate architectural and micro-architectural solutions.
• Leverage agentic AI tools to automate repetitive tasks, accelerate debug, and improve team efficiency.

Requirements

Must-have technical skills and experience to perform the role; followed by desirable qualifications that strengthen candidacy.

• Extensive hands-on experience with UVM, SystemVerilog, Verilog, Python, and C/C++.
• Practical experience with constrained-random stimulus, functional coverage, and assertion-based verification.
• Experience with industry EDA/debug tools (e.g., VCS, Verdi/Debussy, GDB) and strong software engineering practices (version control, code review, maintainable code).
• Proven ability to root-cause complex issues and to debug silicon or silicon-like platforms; experience on shipped silicon preferred.
• Domain knowledge of display pipelines and protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU/SMMU interactions, and system low-power features (clock gating, power domains, retention sequences).
• Effective communicator and self-starter able to work across time zones and organizational boundaries.

• Prior display unit verification experience, including pixel processing and ISO performance testing.
• Experience verifying display protocols end-to-end and validating MMU/SMMU behavior under ISO traffic.
• Experience with HLS-based designs and shaping architectural specifications or micro-architecture decisions.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.