Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Join the Security IP team to lead verification of complex hardware security IPs and processor-based subsystems. You will own block- and subsystem-level verification, develop advanced SystemVerilog/UVM environments, and coordinate with design, architecture, firmware, and validation teams to ensure functional correctness and security.

Role includes debug, coverage closure, support for emulation and post-silicon activities, mentorship of junior engineers, and up to 10% travel.

Experience Level

Senior — typically 4–7 years of experience in digital design verification.

Responsibilities

The main responsibilities include:

• Own block- and subsystem-level verification for security-focused IPs and secure enclave solutions.
• Develop SystemVerilog/UVM verification environments, scoreboards, checkers, assertions, and functional coverage models.
• Create constrained-random and directed tests targeting functional, security, and corner-case behaviors.
• Drive closure using code, functional, and assertion coverage plus regression analysis.
• Debug RTL and simulation failures, perform root-cause analysis, and drive fixes.
• Verify processor-based subsystems by writing C tests and integrating firmware for accelerators, secure boot, and key management functions.
• Support emulation, firmware integration, and post-silicon validation activities.
• Contribute to reusable VIP, automation infrastructure, and verification methodology improvements.
• Mentor junior verification engineers and share best practices.

Requirements

Key must-have technical skills and experience. Preferred items are listed separately.

• 4–7 years of experience in digital design verification (typical).
• Strong proficiency in SystemVerilog and UVM methodology.
• Experience developing reusable verification environments, scoreboards, checkers, and coverage models.
• Deep understanding of constrained-random verification, functional coverage, and Assertion-Based Verification (SVA).
• Experience with RTL simulation and debug tools (examples: VCS, Xcelium, Simvision, Verdi, Questa).
• Proficient scripting skills (Python, Perl, or Tcl) and experience working in Linux environments.
• SoC verification experience, including writing C test cases and verifying processor-based systems (ARM Cortex-M, RISC-V, or similar).
• Familiarity with common SoC interfaces (APB, AHB, AXI, QSPI, UART) and DMA architectures.

Nice-to-have:

• Experience verifying hardware security IPs (AES, SHA, RSA, ECC, post-quantum accelerators, key management, secure storage).
• Familiarity with secure enclave architectures, root-of-trust, secure boot, DICE, or trusted execution environments.
• Experience with formal verification, emulation platforms, and firmware-driven verification.
• Exposure to side-channel/fault-injection mitigation techniques and hardware security concepts.
• Familiarity with AI-assisted engineering or verification productivity tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.