Senior Verification Engineer

Role Overview

This position is for a Senior Verification Engineer focused on developing comprehensive verification IPs for complex interfaces. The role involves a deep understanding of customer requirements and effective collaboration with internal teams and customers.

Position Summary

The Senior Verification Engineer will play a crucial role in the development and enhancement of verification IPs for high-speed interfaces. Active collaboration with design and test engineering partners will be essential to ensure product quality and reliability.

Experience Level

Candidates should possess strong proficiency in verification engineering with several years of hands-on experience in the field. The role requires a solid background in electronic design automation (EDA) and protocols.

Key Responsibilities

• Develop and enhance Questa verification IPs to achieve optimal bug detection and resolution.
• Specify and implement components for various end-user applications.
• Engage with Technical Marketing Engineers (TMEs) and customers to address and resolve issues.
• Utilize knowledge of System Verilog, UVM, and other verification methodologies.

Candidate Requirements

Applicants must have a B.Tech or M.Tech degree in Electronics Engineering or a related field from a recognized institution. They should exhibit strong expertise in verification engineering, along with a solid grasp of bus protocols such as PCIe, USB, and DDR5.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a closely related discipline.