Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Individual-contributor role responsible for planning and executing functional verification for cache and memory-subsystem features, with emphasis on cache coherency, ordering, correctness, and subsystem integration.

The engineer will build and maintain verification environments, write tests and checkers, debug complex failures, and contribute reusable methodology and automation to improve team-wide verification quality and productivity.

Experience Level

Senior — typically requires 3+ years of relevant IP, subsystem, or SoC functional verification experience, preferably with CPU, memory-system, or cache verification.

Responsibilities

Key responsibilities include planning and executing verification activities, building environments, and driving closure of verification risks.

• Develop verification strategies and test plans for cache and memory-subsystem areas.
• Implement and maintain testbenches, checkers, scoreboards, assertions, stimulus, and coverage models for coherency, ordering, flow control, and error scenarios.
• Create and run directed and constrained-random tests to exercise corner cases in coherency, concurrency, backpressure, and integration behavior.
• Analyze failures, isolate root cause, and coordinate fixes across RTL, testbench infrastructure, and test content.
• Collaborate with architecture, design, and verification teams to clarify requirements and improve verification early in the development cycle.
• Write and analyze functional coverage and close coverage holes to ensure verification completeness and signoff readiness.
• Contribute reusable methodology, automation, and debug improvements to raise team productivity and verification quality.

Requirements

Required technical skills and experience, followed by preferred capabilities.

Must-have:

• 3+ years of experience in IP, subsystem, or SoC functional verification, preferably in CPU, memory-system, or cache verification.
• Hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and ability to work across design and verification teams.

Nice-to-have:

• Direct experience verifying cache or memory-subsystem functionality in multicore systems.
• Experience with subsystem integration and protocol interactions across multiple interfaces.
• Familiarity with scripting and automation using Python or similar languages.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.