Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

The Senior UVM Digital Verification Engineer develops and executes verification strategies for FPGA and ASIC digital designs across embedded security, cryptography, signal/image processing, navigation, and communications domains. You will work on block- and chip-level verification, lead small teams, and mentor junior engineers.

Experience Level

Senior — typically requires 5–7 years of relevant experience in digital verification or systems analysis.

Responsibilities

Primary responsibilities include designing and implementing verification environments, driving closure of functional and code coverage, and coordinating with designers and stakeholders.

• Develop verification approaches and author/execute verification plans.
• Design and implement UVM agents and integrate VIP for industry-standard buses.
• Build and run block-level and chip-level UVM testbenches.
• Perform constrained-random testing, coverage-driven verification, and covergroup implementation.
• Use formal analysis tools and assist in formal verification tasks.
• Work with RTL designers to debug simulation issues and close functional/code coverage.
• Conduct code reviews and mentor junior engineers; lead small teams when assigned.
• Identify program/system-level technical risks and execute mitigation strategies.
• Present verification results to support system-level trade-offs and decision-making.

Requirements

Concise list of required skills and desirable skills.

• Must-have: Fluent in SystemVerilog including SVA; recent experience with UVM/UVMF.
• Must-have: Experience with at least one major industry simulator (QuestaSim, Xcelium, VCS).
• Must-have: Practical experience with bus protocols such as DDR3/DDR4 and AMBA AXI.
• Must-have: Strong knowledge of constrained-random testing, coverage-driven methodologies, and experience achieving coverage closure.
• Must-have: Experience with formal analysis tools and scripting (Python, Perl, Bash) and working in a Linux environment.
• Must-have: Proven problem-solving, written/verbal communication, and ability to work in multidisciplinary teams.
• Must-have: Ability to obtain and maintain a U.S. government security clearance (or eligibility).
• Nice-to-have: Experience leading small teams and mentoring engineers; familiarity with additional bus standards or verification frameworks.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or another relevant engineering field is required. A Master's degree is preferred.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.