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Senior UVM Digital Verification Engineer

Draper
August 09, 2026
Full-time
Remote
Worldwide
$82,300 - $220,000 USD yearly
Verification Jobs, Level - Senior

Job Title

Senior UVM Digital Verification Engineer

Role Summary

Senior engineer on Draper’s Digital Design Team responsible for developing and executing verification strategies for FPGA and ASIC designs across embedded security, cryptography, signal/image processing, navigation, and communications domains. Works in multidisciplinary teams to translate requirements into verification and architectural decisions.

Experience Level

Senior — typically 5–7 years of related experience in digital verification or systems analysis; demonstrated ability to lead small teams and mentor junior engineers.

Responsibilities

Primary duties include planning and executing verification, driving solutions to complex problems, and coordinating with designers and stakeholders.

  • Develop verification strategies and author/execute verification plans for block- and chip-level designs.
  • Design and implement UVM testbenches, UVM agents, and instantiate VIP for industry-standard buses.
  • Use constrained-random testing and coverage-driven methodologies to close functional and code coverage.
  • Apply formal analysis tools and integrate descriptive modeling with simulation environments.
  • Collaborate with RTL designers to diagnose and resolve simulation and design issues.
  • Perform code reviews, implement cover groups, and drive coverage closure toward targets.
  • Lead and mentor small engineering teams; provide technical guidance and constructive feedback.
  • Communicate results and trade-offs to engineers, managers, and stakeholders.

Requirements

Required technical skills, experience, and professional abilities. Education requirements are summarized separately below.

  • Must-have: 5–7 years of relevant experience in digital verification, systems analysis, or equivalent.
  • Must-have: Fluent in SystemVerilog (including SVA) and recent practical experience with UVM/UVMF.
  • Must-have: Experience with at least one major simulator (Questa, Xcelium, VCS) and with industry bus standards.
  • Must-have: Hands-on experience with DDR3/DDR4 and AMBA AXI protocols, constrained-random testing, and coverage-driven verification.
  • Must-have: Practical use of formal analysis tools and scripting (Python, Perl, Bash) in a Linux environment.
  • Must-have: Strong analytical, problem-solving, organizational, and communication skills; ability to meet deadlines.
  • Desired: Demonstrated ability to lead small teams and mentor junior engineers.
  • Desired: Experience integrating modeling tools with simulators and working on mixed-signal or multidisciplinary projects.
  • Security: Ability to obtain and maintain a government security clearance is required for selected candidates.

Education Requirements

Bachelor’s degree in Aerospace, Electrical, Mechanical, or another relevant engineering field required. Master’s degree preferred. Equivalent practical experience will be considered.


About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.

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Date Posted: 2026-08-08