Senior Timing Methodology Engineer

Job Title

Senior Timing Methodology Engineer

Role Summary

Define, develop and drive timing, design and power sign-off methodologies for AMD's Adaptive and Embedded Computing Group. Work with architecture, product planning, process, implementation, and product engineering teams to achieve best-in-class power, performance and area (PPA) for monolithic and 2.5/3DIC adaptive SoCs and FPGAs at advanced nodes (2nm and beyond).

Role requires cross-functional collaboration with CAD, foundry, power integrity, and EDA vendors to identify sign-off risks and implement mitigation strategies. Location: San Jose, CA. This role is not eligible for visa sponsorship.

Experience Level

Senior — role expects senior-level experience. No explicit years listed in the posting (typically a senior role implies ~7+ years of relevant experience).

Responsibilities

Primary responsibilities include setting methodology direction and enabling design teams to achieve silicon sign-off targets.

• Define, develop, optimize and drive design, timing and power methodologies for advanced process nodes.
• Develop sign-off and modeling methodologies for monolithic and 2.5/3DIC adaptive SoCs and FPGAs.
• Collaborate with implementation and sign-off teams to close timing and power margin gaps.
• Work with CAD, power integrity, foundry teams and EDA vendors to assess margins, identify sign-off risks, and develop mitigations.
• Translate high-level requirements from product planning, foundry, and stakeholders into actionable guidelines and methodologies for designers.
• Advocate technical solutions and drive adoption across cross-functional teams.

Requirements

Must-have technical skills, plus preferred experience and tool knowledge.

• Proven experience as a custom, physical design, or sign-off engineer.
• Expert user of industry-standard physical design, analysis, and sign-off tools.
• Strong communication and collaboration skills; able to work across architecture, CAD, process and product teams.
• Ability to evaluate margins and sign-off risks and define mitigation strategies with foundry and EDA partners.
• Good programming/scripting skills (Python, Perl, Tcl).
• Experience with FPGA implementation tools (preferred).

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.