Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Intel CorporationJob Title
Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Role Summary
Join Intel Foundry's Design Technology Platform (DTP) on the X-Chip SoC Full-Chip Integration team to develop physical design methodology and drive full-chip SoC integration for testchip vehicles that validate advanced process technologies and support manufacturing readiness.
The role requires collaboration with design, process, and manufacturing partners to deliver scalable, production-oriented layout solutions for advanced technology nodes.
Experience Level
Senior — approximately 5+ years of relevant experience (posting specifies a minimum of 5 years).
Responsibilities
Primary responsibilities include methodology development, full-chip integration, and driving layout convergence for testchip SoCs.
- Develop layout design methodology for testchip development in next-generation process nodes.
- Work with Process Integration, Yield, and QnR to define critical design features to exercise in lead vehicle test chips.
- Establish, oversee, and maintain hierarchical layout design specifications for correct-by-construction integration.
- Build and execute plans to converge hierarchical SoC layouts against aggressive schedules, coordinating with PDK teams.
- Drive physical design convergence: prepare layout hierarchy for tape-in, debug and resolve verification tool issues.
- Collaborate with tool/flow owners and vendors to improve tools and methodologies.
- Coordinate stakeholders to reach execution commit and ensure timely testchip delivery.
Requirements
Must-have technical skills and experience; preferred items listed as additional strengths.
- Experience with physical/layout design in advanced technology nodes.
- Proficiency with layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler.
- Knowledge of design rules and layout constraints in advanced semiconductor processes.
- Experience with floorplanning, hierarchical design integration, and layout verification/debug.
- Strong verbal and written communication skills and ability to work both autonomously and in cross-functional teams.
- Preferred: Experience defining testchip/product design from concept to execution commit.
- Preferred: Experience working with foundry teams to negotiate features to exercise in designs.
- Preferred: Project management skills coordinating and tracking design cycles; prior foundry experience is a plus.
Education Requirements
Master's degree in electrical engineering or a related field is required (posting specifies a Master's). The posting also specifies a minimum of 5 years of relevant experience. Fields referenced: Electrical Engineering or related technical fields.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
