Job Title
Senior Systems Prototyping and Emulation Engineer
Role Summary
Build FPGA prototypes and hardware emulation environments for next-generation GPUs, SoCs, NICs, and switches to enable pre-silicon software development, validation, and performance analysis.
This position sits on the Emulation team and requires coordination across architects, designers, verification, validation, and software teams; the role is onsite in Santa Clara, CA.
Experience Level
Senior level. Typical background: 8+ years with a BS (or equivalent experience) or 6+ years with an MS in relevant engineering fields (see Education Requirements for details).
Responsibilities
Primary responsibilities include bringing up, optimizing, and supporting FPGA prototypes and hardware emulation platforms for complex multi-ASIC systems.
- Create FPGA-friendly RTL partitions and carry designs through synthesis, place-and-route, and emulator compilation.
- Improve prototype and emulator performance; analyze timing and performance bottlenecks; generate bitstreams/images.
- Bring up designs on prototyping and emulation platforms and drive complex debug and problem resolution.
- Release prototypes/emulation environments to internal customers and support debug, validation, and software enablement.
- Define configurations, develop bring-up and test infrastructure, and verify system correctness.
- Realize multi-ASIC system topologies (e.g., DGX) on prototyping platforms and emulators.
- Develop and optimize emulation-friendly validation infrastructures, high-performance software interfaces, and scalable debug methodologies.
Requirements
Must-have technical skills and experience for immediate contribution.
- Proven hands-on experience with FPGA prototyping and hardware emulation flows, architectures, devices, and tools.
- Experience with Synopsys ProtoCompiler or Synplify Premier and Xilinx Vivado; familiarity with Synopsys ZeBu or Siemens Veloce emulation platforms.
- Experience with ASIC design and verification tools (e.g., VCS, Verdi) and typical debug tools (GDB).
- Proficiency in Verilog and SystemVerilog and solid digital design fundamentals.
- Working knowledge of industry protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU–GPU coherency.
- Practical lab FPGA debug experience and familiarity with tools such as Identify or ChipScope and lab equipment (oscilloscopes, logic analyzers).
- Strong C/C++ testbench and transactor development skills; experience optimizing host–emulator communication and transaction throughput at emulation speeds.
- Ability to develop DPI/PLI/SystemC-based interfaces and software infrastructures for high-speed validation, debug, and bring-up on emulation platforms.
- Onsite presence in Santa Clara, CA and ability to collaborate across distributed teams.
Nice-to-have:
- Scripting knowledge (Perl, shell, Tcl, Python).
- Experience with memory bring-up (LPDDR5/6, DDR5/6), high-speed interfaces (USB4/3), or CXL/PCIe bring-up.
- Prior experience with Synopsys HAPS, ZeBu, or Siemens Veloce on high-performance processors or SoCs.
- Experience designing performance-sensitive validation methodologies for large-scale emulation environments.
- Strong documentation, communication, and interpersonal skills.
Education Requirements
BS in Electrical Engineering, Computer Engineering, or a related field (or equivalent practical experience) with ~8+ years of relevant experience, or MS in a related field with ~6+ years of relevant experience. The posting accepts equivalent practical experience in place of a degree.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

Date Posted: 2026-05-20