Senior Synthesis and Implementation Engineer

Job Title

Senior Synthesis and Implementation Engineer

Role Summary

Member of the AI NPU front-end team responsible for translating RTL designs into optimized gate-level netlists and delivering on performance, power and area (PPA) targets for complex digital IP blocks.

Work closely with RTL designers, DFT and physical design teams to achieve timing closure, verify equivalence, reduce power and automate synthesis flows.

Experience Level

Senior — requires 5+ years of relevant experience in digital ASIC/SoC design with a focus on synthesis and front-end implementation.

Responsibilities

Core responsibilities include front-end synthesis, timing and power optimization, formal equivalence and flow automation.

• Perform logical and physical synthesis of RTL blocks and subsystems, including hierarchical synthesis flows.
• Develop and implement timing constraints (SDC) and optimization strategies to meet target frequencies.
• Run static timing analysis (STA), identify critical paths and drive timing closure with design teams.
• Execute formal equivalence checking (LEC) to ensure RTL-to-gate netlist correctness.
• Analyze and optimize front-end power using UPF-aware flows and power analysis tools.
• Estimate and optimize area to satisfy aggressive PPA requirements.
• Collaborate with RTL, DFT and physical design engineers for integration and hand-off.
• Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and analysis.
• Evaluate and integrate CAD tools and methodologies to improve quality and efficiency.
• Document constraints, methodologies and analysis results.

Requirements

Must-have technical skills and experience; nice-to-have items noted separately.

• Must have: Proficiency with industry synthesis tools (for example Synopsys Design Compiler/Genus or Cadence Genus).
• Strong knowledge of static timing analysis and tools (for example Synopsys PrimeTime or Cadence Tempus).
• Experience with formal verification tools (for example Synopsys Formality or Cadence Conformal).
• Solid RTL design skills in Verilog/SystemVerilog.
• Experience with UPF/low-power design techniques and power analysis concepts.
• Proficiency in scripting for automation (Tcl, Python, Perl).
• Proven problem-solving ability and attention to detail; able to work across time zones in a collaborative team.
• Nice to have: Experience with physical synthesis, floorplanning and DFT principles.

Education Requirements

Bachelor's or Master's degree in VLSI, Electronics Engineering or a related technical field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.