Senior Synthesis and Front-End Implementation Engineer

Job Title

Senior Synthesis and Front-End Implementation Engineer

Role Summary

Work on synthesis and front-end implementation for AI NPU digital IP, converting RTL into optimized gate-level netlists and ensuring designs meet performance, power, and area objectives.

Member of the AI NPU team responsible for synthesis flows, timing closure, front-end power analysis, formal equivalence, automation, and cross-discipline integration with RTL, DFT and physical design teams.

Experience Level

Senior; typically requires 5+ years of relevant experience in digital ASIC/SoC design focused on synthesis and front-end implementation.

Responsibilities

Primary responsibilities include translating RTL into optimized netlists and ensuring timing, power, and area objectives are achieved.

• Perform logical and physical synthesis (including hierarchical synthesis) for digital blocks and sub-systems.
• Develop and implement timing constraints (SDC) and drive timing closure.
• Conduct static timing analysis, identify critical paths, and collaborate with designers to resolve timing issues.
• Execute formal equivalence checks between RTL and synthesized netlists.
• Analyze and optimize front-end power and perform area estimation and optimization to meet PPA targets.
• Collaborate with RTL designers, DFT engineers, and physical design teams for hand-off and integration.
• Develop and maintain automation scripts (Tcl, Python, Perl) for synthesis flows and analysis.
• Evaluate and integrate CAD tools and methodologies to improve efficiency and quality.
• Document design constraints, methodologies, and analysis results.

Requirements

Must-have technical skills and experience:

• 5+ years in digital ASIC/SoC design with synthesis/front-end implementation experience.
• Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler / Fusion Compiler, Cadence Genus).
• Strong experience with static timing analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus).
• Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal).
• Solid knowledge of Verilog/SystemVerilog for digital design.
• Familiarity with scripting languages for automation (Tcl, Python, Perl).
• Understanding of UPF, low-power design techniques and power analysis concepts.
• Strong problem-solving skills, attention to detail, and effective communication across teams and time zones.

Nice-to-have:

• Experience with physical synthesis and floorplanning.
• Knowledge of DFT (Design for Testability) principles.

Education Requirements

Bachelor's or Master's degree in VLSI, Electronics Engineering, or a related field.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.