Senior Syn/STA Engineer

Job Title

Senior Syn/STA Engineer

Role Summary

Lead block-level digital synthesis and static timing analysis (STA) efforts to achieve timing closure and optimize power for complex SoC blocks. Collaborate with RTL designers, DFT and physical-design teams to resolve QoR and timing issues and mentor junior engineers.

The role focuses on synthesis, timing constraints, STA signoff, timing ECOs, and automation for advanced process nodes (16nm and below).

Experience Level

Senior — typically 4–6 years of relevant experience in synthesis and STA; experience mentoring engineers and leading block-level timing closure.

Responsibilities

Primary responsibilities include synthesis and timing signoff activities across block and subsystem levels.

• Develop and maintain complex timing constraints for IP, subsystem and full-chip flows.
• Perform STA signoff and timing closure for high-speed SoC designs in advanced process nodes (16nm and below).
• Analyze timing violations, root-cause issues across synthesis, placement, routing, and propose fixes.
• Implement timing ECOs using tool-driven and manual techniques.
• Collaborate with RTL, DFT, and physical design teams on RTL-to-GDS flow issues and power-aware timing.
• Automate timing analysis and flows using Tcl/Perl/Python scripting.
• Mentor junior engineers and communicate technical status across teams.
• Travel up to approximately 10% as required.

Requirements

Key must-have skills and desirable experience.

• Must-have: Hands-on experience in digital synthesis, STA, and timing constraints development for complex blocks.
• Must-have: Proven ability to achieve timing closure and perform signoff on complex designs.
• Must-have: Proficiency with timing analysis tools and familiarity with synthesis, LEC, PD and signoff tool commands and constructs.
• Must-have: Strong debugging and troubleshooting skills for timing/QoR issues; experience with timing ECOs.
• Must-have: Scripting/automation skills (Tcl, Perl, Python).
• Nice-to-have: Experience with floor-planning, placement, CTS, routing, extraction, physical verification and EM/IR flows.
• Nice-to-have: Familiarity with Scan/DFT modes and timing and power optimization techniques.
• Good communication and cross-collaboration skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related technical field — or equivalent practical experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.