Senior Subsystem Design Verification Engineer

Job Title

Senior Subsystem Design Verification Engineer

Role Summary

Verify complex SoC subsystems and drive subsystem-level verification from planning through closure. You will build reusable verification environments, develop test plans and automation, and collaborate with architecture, design, firmware, emulation, FPGA, and validation teams.

This role focuses on delivering thorough functional, integration, stress, and performance verification for interconnects, memory interfaces, peripherals, power management, and software-visible features.

Experience Level

Senior — the posting specifies 4–9 years of experience in IP or subsystem verification.

Responsibilities

Primary responsibilities include planning and executing subsystem verification, developing reusable verification assets, and driving closure across functional and coverage metrics.

• Develop and execute verification strategies for subsystem designs and IP integration.
• Verify subsystem functionality for interconnects, memory interfaces, peripherals, power management, and software-visible features.
• Validate functionality under functional, integration, stress, and performance scenarios.
• Own verification deliverables from planning through closure, ensuring quality and schedule commitments are met.
• Architect, develop, and maintain reusable verification environments, VIPs, methodologies, and automation.
• Create verification plans, test methodologies, test cases, and coverage-closure strategies.
• Drive functional, code, toggle, assertion, and coverage closure; debug RTL, testbench, integration, and system-level issues.
• Collaborate with architecture, design, firmware, emulation/FPGA, validation, and post-silicon teams.
• Leverage automation, scripting, and AI-assisted workflows to improve verification productivity.
• Contribute to methodology improvements, documentation, and engineering best practices.

Requirements

Key technical skills and experience required and preferred for successful performance in this role.

• Must-have: Strong knowledge of Verilog, SystemVerilog, UVM, and modern verification methodologies.
• Must-have: Solid understanding of subsystem architecture, integration, AMBA protocols, memory hierarchy, and verification flows.
• Must-have: Experience with C/C++ and scripting for test automation, coverage closure, and RTL/testbench debugging.
• Must-have: Proven ability to debug complex RTL, testbench, and integration issues and to deliver verification closure.
• Must-have: Strong analytical, written, and verbal communication and collaboration skills.
• Nice-to-have: Experience with multimedia, security, PCIe, networking, storage, or memory subsystems.
• Nice-to-have: Knowledge of Arm architecture and deeper AMBA protocol experience.
• Nice-to-have: Experience with UPF, formal verification, emulation, FPGA, or gate-level simulation.
• Nice-to-have: Experience developing reusable verification IPs, automation frameworks, and AI-assisted verification flows.

Education Requirements

Bachelor's or Master's degree in a relevant engineering discipline (as stated in the posting).

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.