Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Job Title

Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Role Summary

Technical owner for Static Timing Analysis (STA) flows and timing-modeling methodology across ASIC, custom, semi-custom IP, and FPGA timing domains. Lead a small engineering team to design, release, and support production-grade timing flows and characterization toolchains.

Work spans transistor-level simulation and cell characterization through timing model generation and sign-off flows; represent timing methodology across design, physical design, technology, reliability, and EDA vendors.

Experience Level

Senior — typically requires 10+ years of relevant professional experience in semiconductor design automation, CAD/EDA, or ASIC/custom IC design.

Responsibilities

Deliver and maintain STA methodology, production flows, regressions, and automation; lead technical decisions and mentor engineers.

• Design, implement, and release production STA flows, regressions, and automation for block- and full-chip sign-off.
• Own timing-modeling methodology from characterization through Liberty/model generation used by design and FPGA toolchains.
• Debug timing issues with design teams during tape-outs; triage support tickets and provide training and documentation.
• Drive methodology modernization and greenfield initiatives, including flow architecture and regression infrastructure.
• Represent timing domain in cross-functional forums and with major EDA vendors; evaluate tool capabilities and influence roadmaps.
• Mentor engineers and set technical direction for timing methodology and tool deployment.
• Apply and integrate AI/ML techniques into timing, characterization, and flow automation where beneficial.

Requirements

Must-have skills and experience.

• 10+ years professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or closely related domain with hands-on experience deploying production DA/CAD flows.
• 10+ years working with Static Timing Analysis and timing sign-off methodology, including constraints, MCMM, crosstalk, OCV, timing derates, and advanced process-node timing issues.
• 10+ years experience with industry-standard timing analysis, cell characterization, and/or SPICE circuit simulation tools; able to evaluate tool technical capabilities and make methodology decisions.
• Strong software/automation skills: production-quality development with Python, Tcl, shell scripting, and solid understanding of algorithms and data structures.
• Proven experience owning and releasing production-grade flows: flow architecture, regression infrastructure, validation, deployment, maintenance, and user support.
• Demonstrated technical leadership: set methodology direction, drive complex technical decisions, establish best practices, and mentor engineers without formal management authority.
• Proven cross-functional collaboration with ASIC/custom design, physical design, technology/process, reliability, and EDA vendors; experience supporting designs through tape-out/sign-off.

Nice-to-have.

• Ownership of block-level and/or full-chip STA methodology through multiple production tape-outs.
• Advanced cell characterization and Liberty model generation experience (LVF, POCV, statistical/variation-aware modeling).
• Transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flow experience.
• Experience developing or supporting FPGA timing models and customer-facing timing collateral.
• Expertise in timing reliability, aging, derating, electromigration, or related reliability-aware methodologies.
• Experience with advanced-node timing challenges: variation, signal integrity, crosstalk, multi-voltage or complex MCMM sign-off.
• Experience applying AI/ML to design automation (runtime prediction, corner reduction, automated debug) and leading methodology modernization initiatives.

Education Requirements

Bachelor's degree required in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Master's or Ph.D. in a similar technical field is preferred.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.