Senior Staff Verification Engineer, High-Speed Interface IP

Job Title

Senior Staff Verification Engineer, High-Speed Interface IP

Role Summary

Design and deliver scalable SystemVerilog/UVM verification environments, testbenches, and coverage models for DesignWare high-speed interface IP cores. The role focuses on functional closure, regression automation, and protocol-compliant verification for IP that targets commercial, enterprise, and automotive markets.

You will work on a global verification R&D team in a multi-site engineering organization, driving verification methodology, reusable VIP, and cross-site collaboration to ensure production-quality silicon-proven IP.

Experience Level

Senior-level; typically 8+ years of hands-on ASIC or IP verification experience (or equivalent industry experience).

Responsibilities

Primary responsibilities include architecting verification environments, developing comprehensive tests, and driving closure for high-speed interface IP.

• Architect and implement SystemVerilog/UVM verification environments, checkers, and functional coverage models for high-speed interface IP.
• Create and execute test plans that cover unit- and system-level requirements; write assertions and test cases.
• Build and maintain regression suites using industry simulators (VCS, NC, MTI); analyze coverage and drive toward functional closure.
• Debug complex protocol interactions and RTL issues; collaborate with design engineers to identify root causes.
• Automate verification flows and reporting using scripting (Perl, TCL, Python).
• Contribute to verification methodology improvements, VIP development, and integration with formal tools.
• Collaborate with global verification teams to align strategies and share reusable components.

Requirements

Required technical skills and experience. Items marked "Nice-to-have" are additional advantages.

• Deep expertise in SystemVerilog and UVM/OVM/VMM methodologies; proven ability to build verification environments from scratch.
• Strong experience with industry simulators (VCS, NC, MTI) and waveform/log-based debug techniques.
• Working knowledge of high-speed interface protocols such as MIPI-I3C, UFS, AMBA, PCIe, USB, Ethernet, or DDR; ability to learn new protocols quickly.
• Proficiency in scripting for automation and flow development (Perl, TCL, Python).
• Proven experience with functional coverage-driven verification and meeting quality/coverage metrics in production IP projects.

Nice-to-have

• Exposure to formal verification techniques and VIP development.
• Experience mentoring junior engineers and working across multi-site teams.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) with ~8+ years experience, or Master of Science in Electrical Engineering (MSEE) with ~5+ years experience in ASIC/IP verification; or equivalent practical industry experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.