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Senior Staff Verification Engineer for Worldguard

SiFive
July 01, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Verification Jobs, Level - Senior

Job Title

Senior Staff Verification Engineer for Worldguard

Role Summary

Lead verification of processor and security IP for the Worldguard product line. Own verification strategy, test plans, and scalable testbenches to ensure functional correctness and coverage closure for CPU and security features.

Work on a cross-functional verification team in Bengaluru to drive verification from planning through sign-off.

Experience Level

Senior β€” typically 10+ years of experience in design verification, preferably with CPU verification experience.

Responsibilities

Key responsibilities include defining verification strategy, building test environments, and driving closure.

  • Define verification plans from architectural specifications, including test cases, checkers, and coverage goals.
  • Design and implement scalable, reusable SystemVerilog/UVM testbenches and environments.
  • Write constrained-random sequences and directed tests to exercise corner cases and security features.
  • Perform root-cause analysis on RTL failures and testbench issues using waveform tools.
  • Track and close functional and code coverage; author covergroups and coverpoints.
  • Own delivery for security architecture verification and related features.
  • Collaborate with architecture, RTL, and validation teams during integration and bring-up.

Requirements

Must-have technical skills and experience; concise listing of essentials and helpful additions.

  • Must-have: 10+ years in design verification (DV), preferably CPU verification; strong SystemVerilog and UVM proficiency.
  • Must-have: Strong object-oriented programming skills; experience writing tests in C for processor-based verification.
  • Must-have: Demonstrable knowledge of CPU microarchitecture and experience with CPU architectures (RISC-V, ARM, or x86).
  • Must-have: Experience with bus protocols such as AXI; familiarity with bus VIPs and integration.
  • Must-have: Experience debugging complex RTL/testbench issues with waveform viewers and other debug tools.
  • Nice-to-have: Scripting experience (Python/Perl), familiarity with PCIe, experience with third-party VIPs, and prior security-architecture verification experience.

Education Requirements

Bachelor's or Master's degree in Engineering is specified in the posting (e.g., B.E./B.Tech or M.E./M.Tech); the posting pairs the degree expectation with the 10+ years of DV experience.


About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.

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Date Posted: 2026-06-30