Senior/Staff Verification Engineer
RenesasJob Title
Senior/Staff Verification Engineer
Role Summary
Lead functional verification activities for complex digital ICs used in automotive and industrial applications. You will define verification strategies, implement SystemVerilog/UVM environments, drive coverage-driven sign-off, and improve verification methodology and automation.
Work as part of a verification team, collaborate closely with design engineers, and mentor junior engineers to raise overall verification quality.
Experience Level
Senior level. Typical guidance: 5+ years of digital functional verification experience (3+ years with a relevant Master's degree).
Responsibilities
Primary responsibilities include planning, implementation, execution, and sign-off of verification tasks:
- Analyze requirements, architectures, and design specs to define verification strategies, risks, dependencies, and acceptance criteria.
- Create and maintain verification plans with requirements traceability and coverage objectives.
- Develop and enhance reusable SystemVerilog/UVM verification environments (agents, sequences, scoreboards, reference models, coverage).
- Design and run constrained-random, directed, error-injection, assertion-based, and formal verification tests.
- Drive regression runs, debug verification and design issues, and collaborate with design teams to close defects.
- Measure and close functional, code, and assertion coverage gaps to meet sign-off criteria.
- Contribute to system-level verification, automation, process improvements, and mentor junior engineers.
Requirements
Must-have technical skills and experience; desirable items listed separately.
- 5+ years of digital functional verification experience (3+ years with a relevant Master's degree is acceptable).
- Strong expertise in SystemVerilog and hands-on experience developing and debugging UVM-based verification environments.
- Experience with constrained-random and coverage-driven verification methodologies, regression management, and verification planning.
- Ability to translate specifications into verification plans, coverage models, test strategies, and verification reports.
- Good knowledge of digital design fundamentals, interfaces, clock/reset architectures, simulation, and debug workflows.
- Strong communication, collaboration, and mentoring skills; fluent in spoken and written English.
Nice-to-have:
- Experience with Assertion-based verification (SVA) and/or formal verification techniques.
- Experience with automation tools and reusable verification methodology development.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field - or equivalent industry experience. (Education equivalence wording appears in the source: "or equivalent industry experience").
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
