Senior Staff Software/Firmware Engineer - RISC-V Validation Backbone

Job Title

Senior Staff Software/Firmware Engineer - RISC-V Validation Backbone

Role Summary

Lead integration and validation of embedded RISC-V MCU subsystems and firmware to enable software-driven validation of high-speed PHY/IP in lab and silicon environments. The role sits within Central System Engineering and partners with RTL, validation, and architecture teams to deliver scalable firmware and automation for SoC bring-up and PHY validation.

The position focuses on MCU/SoC integration, low-level firmware development (bare-metal and RTOS), system bring-up and cross-domain debugging, and building firmware-driven validation frameworks and automation.

Experience Level

Senior — requires significant experience (listed requirement: 8+ years in embedded systems, firmware, or SoC development).

Responsibilities

The role is responsible for RISC-V MCU integration, firmware development for PHY validation, system bring-up, validation automation, and cross-functional collaboration to expand coverage and reuse.

• Lead integration of RISC-V cores into chip validation environments and define MCU subsystem architecture (memory map, boot flow, execution environment).
• Integrate and validate system interconnects (AHB/AXI-lite) and memory hierarchy (ROM/SRAM); implement interrupt architecture (PLIC, CLINT).
• Develop bare-metal and RTOS-based firmware for PHY/IP control, calibration, training, and tuning algorithms.
• Build reusable firmware frameworks for register-level control, test sequencing, automation, logging, diagnostics, and error handling.
• Lead silicon and pre-silicon bring-up, debug cross-domain HW/FW/PHY issues, and drive root-cause analysis for system-level failures.
• Integrate firmware into validation automation to enable unified validation across simulation, emulation/FPGA, and silicon; develop firmware-driven test scenarios and infrastructure for automated execution and result collection.
• Transition validation toward software-driven closed-loop validation and define coverage for functional behavior, corner cases, stress, recovery, and error handling.
• Maintain RISC-V toolchain and debug workflows; drive automation for firmware build, deployment, and regression execution.

Requirements

Must-have technical skills and experience required for immediate contribution are listed first, followed by desirable skills.

• Must-have: 8+ years of experience in embedded systems, firmware, or SoC development.
• Strong proficiency in C/C++ and bare-metal programming; experience with boot flows, startup code, and linker scripts.
• Experience with memory-mapped I/O, register-level programming, interrupt handling, and real-time constraints.
• Hands-on experience debugging HW/SW integration issues using silicon, FPGA, or RTL simulation.
• Solid understanding of computer architecture fundamentals (CPU, memory hierarchy, buses).
• Nice-to-have: Experience with RISC-V systems or similar MCU architectures (ARM Cortex-M), AHB/AXI-lite bus integration, familiarity with PLIC/CLINT interrupt systems, PHY/SerDes bring-up or validation, RTOS experience (FreeRTOS, Zephyr), and exposure to silicon bring-up or post-silicon validation.
• Strong plus / differentiators: Experience building firmware-driven validation frameworks, simulation/emulation workflows (RTL co-sim, FPGA prototyping), closed-loop control systems (calibration/tuning), or hardware verification/validation environments.

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.