Senior Staff SoC Design Verification Engineer

Job Title

Senior Staff SoC Design Verification Engineer

Role Summary

Work within the SoC Design Verification organization to plan and execute verification for complex SoC, subsystem, and IP designs. Collaborate with architects, RTL designers, integration, synthesis, firmware, emulation, and post-silicon teams to achieve pre-silicon release readiness and support post-silicon debug.

Experience Level

Senior-level (title: Senior Staff). Years-of-experience expectations vary by degree and role seniority; see Education Requirements for degree/experience combinations.

Responsibilities

Primary responsibilities include verification planning, testbench and test development, simulation and coverage closure, and cross-functional debug and signoff.

• Translate product and block specifications into verification plans, test scenarios, functional coverage, and signoff criteria.
• Develop and maintain SystemVerilog/UVM testbenches, sequences, drivers, monitors, scoreboards, assertions, and reusable verification components.
• Create directed, constrained-random, assertion-based, and coverage-driven tests for functional, corner-case, error, reset, power-state, security, and performance scenarios.
• Verify RTL integration, interfaces, registers, interrupts, clocks/resets, power-management behavior, interconnect/coherency, and subsystem connectivity.
• Run and debug simulation, regression, lint, CDC/RDC, formal, emulation, FPGA, and gate-level verification flows as applicable; analyze failures and perform root-cause debug.
• Define, track, and close functional, code, assertion, toggle, and coverage metrics; identify verification gaps and improve stimulus quality.
• Collaborate with RTL, architecture, integration, and synthesis teams to identify design issues early and drive defect resolution.
• Support emulation readiness, firmware bring-up, SoC integration testing, pre-silicon release, and post-silicon debug preparation.
• Automate regression, debug, and reporting tasks using scripting (Python, Perl, Tcl, Shell) and document verification plans, results, and release recommendations.

Requirements

Must-have technical skills and experience for the role. Senior-staff candidates are expected to lead verification efforts and influence methodology and delivery.

• Hands-on experience with SystemVerilog and UVM-based verification environments.
• Proven experience with simulation, regression execution, waveform debug, and functional coverage analysis.
• Solid understanding of digital design fundamentals: RTL, finite-state machines, protocols, clocks/resets, and SoC architecture.
• Experience debugging across RTL, testbench, generated collateral, tools, and environments.
• Experience with verification flows and tools (simulation, lint, CDC/RDC, formal, emulation, FPGA, gate-level) and coverage closure practices.
• Scripting and automation skills (Python, Perl, Tcl, Shell) to improve regression and debug productivity.
• Strong analytical, communication, and teamwork skills; ability to coordinate cross-functional issue resolution.
• For senior/staff/principal roles: demonstrated technical leadership, methodology ownership, and mentoring of engineers.

Nice-to-have:

• Experience verifying complex SoCs, processors, interconnects, memory systems, peripherals, security features, or low-power designs.
• Familiarity with AMBA protocols (AXI, AHB, APB), interrupts, DMA, coherency, NoC/interconnect behavior, and register interfaces.
• Experience with formal verification, assertion-based verification, CDC/RDC analysis, emulation, FPGA prototyping, or power-intent verification.
• Experience with internal or commercial EDA tools for simulation, lint, CDC/RDC, formal, emulation, and coverage analysis.

Education Requirements

Options provided in the posting: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; Master's or PhD in those fields are listed as preferred/alternate. The posting defines equivalent degree/experience combinations: Bachelor's + 4+ years hardware-engineering experience; Master's + 3+ years; PhD + 2+ years. (Earlier sections also reference 3+ years of relevant ASIC/SoC/IP/FPGA or hardware verification experience in general.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.