Senior Staff SoC Design Engineer

Job Title

Senior Staff SoC Design Engineer

Role Summary

Senior Staff SoC Design Engineer responsible for SoC microarchitecture, RTL development, and full-chip integration for high-performance data-center designs. The role works within a team developing next-generation photonic-enabled interconnect and SoC subsystems for accelerated computing, collaborating closely with verification, physical design, IP, and architecture teams.

This position focuses on implementing and integrating complex IP across subsystems to meet performance, power, and area (PPA) targets and to enable high-bandwidth, low-latency system-level interconnects.

Experience Level

Senior-level. Typical experience guidance in the posting: 5–10 years with a Bachelor's degree, or 3–5 years with a Master’s degree or PhD.

Responsibilities

Key responsibilities include microarchitecture, RTL delivery, integration, and cross-team coordination to achieve tape-out quality SoC implementations.

• Define microarchitecture and develop SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic (reset, clocking, power management).
• Integrate processor clusters, memory controllers (HBM/DDR), and high-speed interfaces; specify interfaces, data flow, and system-level behavior.
• Collaborate with verification to review test plans, support functional debug, and close coverage gaps.
• Run standard front-end checks (lint, CDC/RDC), define timing constraints, and work with synthesis and physical design to meet implementation requirements.
• Coordinate with IP, SerDes, and analog teams to resolve subsystem-level integration issues.
• Contribute to design methodology improvements, integration workflows, and provide technical guidance to other engineers.
• Support cross-functional efforts to integrate photonic/optical interfaces and system-of-chip interconnect solutions.

Requirements

Must-have technical skills and domain experience.

• Proven track record delivering complex SoCs to tape-out and working across subsystem boundaries.
• Strong RTL design skills in SystemVerilog and hands-on SoC integration and debug experience.
• Familiarity with AMBA protocols (AXI) and SoC interconnect architectures.
• Experience with clock/reset design, CDC, and timing constraints; understanding of RTL implications for physical implementation.
• Experience with memory interfaces and high-speed SerDes integration (HBM/DDR).
• Scripting experience for automation (Python or Tcl).
• Preferred: exposure to emerging interconnect standards such as UCIe and UALink.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of relevant experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field with 3–5 years of relevant experience. (Degree requirements presented in original posting.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.