Senior Staff RTL Design Engineer - DDR/LPDDR/HBM

Job Title

Senior Staff RTL Design Engineer - DDR/LPDDR/HBM

Role Summary

Design lead responsible for RTL micro-architecture, implementation, and integration of high-performance DDR/LPDDR/HBM memory subsystems for SoC products.

Works within the Data Centre Engineering (Compute & Storage) group on custom ASICs, collaborating with architecture, verification, physical design, firmware and validation teams to deliver production silicon.

Experience Level

Senior — position indicates senior/staff level. The posting specifies ~8+ years of relevant RTL design experience.

Responsibilities

Accountable for end-to-end delivery and technical leadership in memory subsystem RTL design.

• Define subsystem micro-architecture and drive RTL implementation and integration for DDR/LPDDR/HBM designs.
• Translate architecture requirements into robust RTL in collaboration with architecture teams.
• Coordinate with design verification on test plans, debugging, and coverage closure.
• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Improve design quality, enforce coding best practices, and promote reuse across projects.
• Participate in design and milestone reviews and cross-functional technical discussions.
• Mentor junior designers and provide technical leadership within the memory design domain.

Requirements

Key technical and practical skills required for successful performance in this role.

• Must-have: Proven delivery of complex Memory IP or subsystems from architecture through RTL closure (end-to-end DDR/LPDDR/HBM subsystem RTL design and sign-off).
• Must-have: Strong hands-on SystemVerilog/Verilog RTL development and subsystem-level debugging (functional and performance).
• Must-have: Deep knowledge of DDR/LPDDR/HBM protocol architecture including link, transaction, and PHY interaction layers.
• Must-have: Experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Must-have: Experience with clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Must-have: Experience with lint, CDC/RDC analysis, synthesis, and design sign-off flows.
• Must-have: Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor/Siemens) and version control systems (GIT, SVN).
• Must-have: Proficiency in scripting for automation and flows (Tcl, Perl, Python).
• Must-have: Eligibility to access export-controlled technology as required by U.S. export regulations (may require export license review).
• Nice-to-have: Prior experience mentoring teams, driving reuse frameworks, or contributing to cross-project design standards.

Education Requirements

Bachelor's or Master’s degree in Electronics / Electrical Engineering (or closely related technical field) is specified in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.