Senior Staff RTL Design Engineer

Job Title

Senior Staff RTL Design Engineer

Role Summary

Work on SoC microarchitecture, RTL design, and full-chip integration for high-performance custom SoCs. The role focuses on implementing and integrating complex IP, meeting performance/power/area targets, and driving front-end design flow from architecture through design sign-off.

You'll collaborate with verification, physical design, architecture, and IP teams to ensure correct functionality and PPA compliance for production-quality silicon.

Experience Level

Senior-level. Typical experience: 8–12 years with a Bachelor's degree; 5–10 years with a Master's or PhD.

Responsibilities

Main responsibilities include RTL design, integration, and cross-team coordination for SoC-level blocks.

• Define microarchitecture and develop Verilog/SystemVerilog RTL for SoC components (interconnects, memory interfaces, global reset/clock/power logic).
• Integrate IP across subsystems and resolve subsystem-level issues with IP teams.
• Collaborate with verification teams: review test plans, support functional debug, and help close coverage gaps.
• Run and interpret standard design checks (lint, CDC/RDC); define timing constraints and work with synthesis and physical design to meet implementation targets.
• Support synthesis, static timing closure, formal verification, gate-level simulation, and block-level functional verification activities.
• Contribute to design methodology, improve integration workflows, and provide technical guidance and mentorship to other engineers.

Requirements

Must-have technical skills and experience for the role.

• Must-have: Strong micro-architecture and logic design skills for complex SoC/ASIC products.
• Must-have: Hands-on RTL design experience and proficiency with front-end design tools and methodologies.
• Must-have: Experience with synthesis, static timing closure, formal verification, and gate-level simulations.
• Must-have: Experience with multi-clock designs, DFT, resets, LEC, and lint flows.
• Must-have: Proficiency in scripting (Python) for design automation and flow development.
• Must-have: Experience designing for high-speed, low-power, and area-optimized implementations.
• Nice-to-have: Familiarity with industry-standard bus protocols (AXI, AHB, APB).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field with ~8–12 years of relevant professional experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or a related field with ~5–10 years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.