Senior Staff / Principal SoC Floorplan Lead

Job Title

Senior Staff / Principal SoC Floorplan Lead

Role Summary

Own the top-level physical implementation for next-generation AI and data-center SoCs, bridging architecture, RTL, and physical design to deliver optimal power, performance, and area (PPA).

Collaborate with chip architects, RTL leads, packaging, and AMS teams to drive floorplan decisions from concept through tape-out in a fast-paced startup environment.

Experience Level

Senior-level — typically 12+ years in physical design with at least 3 years leading SoC-level floorplanning or acting as the primary owner.

Responsibilities

Primary responsibilities include top-level floorplan ownership, cross-team collaboration, and methodology development for large AI/Data Center chips.

• Own SoC-level floorplan from concept through tape-out on advanced nodes (e.g., 5nm, 3nm).
• Provide early physical feasibility feedback to Architecture and RTL; drive block partitioning, shape optimization, and data-flow planning.
• Lead bump planning, IO ring definition, and die-package co-optimization for flip-chip and advanced packaging.
• Manage placement and custom routing strategies for Analog/Mixed-Signal IP, high-speed SerDes, PLLs, and sensitive clock distributions.
• Design and analyze top-level power delivery network (PDN) to support high-current AI workloads and minimize IR drop.
• Define macro placement, pin assignments, and feedthroughs to optimize global timing and routing congestion.
• Develop and maintain scalable floorplanning workflows, scripts, and automation for a lean engineering team.

Requirements

Must-have technical skills and experience to perform the role; preferred items listed separately.

Must-have

• 12+ years hands-on experience in physical design SoC floorplanning, with at least 3 years as a lead or primary owner of SoC-level floorplanning.
• Proven record of taping out large, complex chips for Data Center, Networking, or AI/ML domains.
• Deep understanding of how RTL and micro-architectural choices affect physical PPA and implementation.
• Experience with bump planning, flip-chip packaging constraints, and die-to-package co-optimization.
• Experience integrating analog/mixed-signal IP, shielding, and custom routing constraints.
• Expertise with industry-standard physical design tools (e.g., Cadence Innovus).
• Experience designing and analyzing top-level PDN and addressing IR drop for high-current designs.
• Experience building floorplanning automation and workflows using scripting (Tcl, Python).
• Proven ability to take ownership and execute in a fast-moving startup environment.

Nice-to-have

• Experience with multi-die/chiplet integration (2.5D, 3D packaging, interposers, UCIe).
• Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics.
• Additional scripting/build skills (Perl, Makefile) and broader automation toolchain experience.

Education Requirements

BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.