Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon

Job Title

Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon

Role Summary

Own physical layout for electronic ICs (EICs) and support photonic IC (PIC) layout and EIC–PIC integration for a production optical interconnect product. Work with cross‑site teams in Singapore, the US, and India to deliver high‑speed analog and mixed‑signal silicon for AI data‑center interconnects.

You will be the senior on‑site layout authority, responsible for layout quality, parasitic closure, and driving tape‑out readiness.

Experience Level

Senior-level. Expect 8+ years of experience in custom analog, RF, or high‑speed mixed‑signal IC layout, with multiple tape‑outs taken to silicon.

Responsibilities

Key responsibilities include block and top‑level layout, physical closure, photonics support, and establishing layout methodology.

• Own floorplan and layout for high‑speed analog/mixed‑signal blocks (TIAs, drivers, SerDes front ends, PLLs, references and bias).
• Execute device‑level matching and symmetry: common‑centroid, dummies, shielding, guard rings, substrate isolation.
• Route high‑speed signal paths controlling impedance, coupling, and return paths; lay out inductors, transformers, and transmission lines and iterate with EM simulation.
• Manage chip finishing: pad rings, bump/pillar maps, seal rings, density fill, and top‑level assembly to tape‑out.
• Drive parasitic‑aware layout and close the loop between extraction results and schematic assumptions.
• Own electromigration and IR drop closure: power grid construction, current density analysis, and verification over temperature and lifetime.
• Take blocks through DRC, LVS, antenna, DFM, ESD and latch‑up checks to sign‑off.
• Support PIC layout and EIC–PIC integration: waveguide routing, modulator and photodetector electrode co‑layout, and micro‑bump/pillar alignment for interposers and multi‑die assemblies.
• Set and document layout standards, PDK/tech file evaluation, automation and review practices; mentor junior layout engineers.

Requirements

Must‑have technical skills and experience; preferred items listed separately.

• 8+ years in custom analog, RF, or high‑speed mixed‑signal IC layout with multiple tape‑outs to silicon.
• Expert Cadence Virtuoso experience, including Layout XL and constraint‑driven flows.
• Deep parasitic awareness and the ability to map schematic/spec to critical nets and layout choices.
• Working command of electromigration and IR drop fundamentals, power grid design, and verification checks.
• Electromagnetics fundamentals for on‑chip structures: inductors, transformers, transmission lines, coupling and shielding.
• Physical verification fluency: Calibre or PVS for DRC/LVS and parasitic extraction using QRC, StarRC, or equivalent.
• Willingness to overlap with US and India hours during tape‑out crunches.

Nice‑to‑have / preferred:

• SiGe BiCMOS layout experience and related passive/isolation practices.
• Advanced FinFET CMOS layout at 7nm and below (multi‑patterning, grid constraints, DRC complexity).
• Photonic IC layout experience (waveguide routing, curvilinear geometry, photonics PDK rules) and hands‑on silicon photonics layout on a foundry platform.
• PCell development and PDK integration in Virtuoso SKILL or Python; experience with gdsfactory, KLayout, or IPKISS.
• 2.5D/3D integration, interposers, micro‑bump and pillar arrays, and co‑packaged optics assembly experience.
• Direct experience with optical front‑end blocks (TIA, modulator driver, high‑speed serial links).
• Experience establishing layout methodology for a new product line; scripting for layout automation (SKILL, Python).

Education Requirements

Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands‑on layout experience (explicitly accepted as an alternative).

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.