Senior Staff / Principal Engineer, Digital Verification

Job Title

Senior Staff / Principal Engineer, Digital Verification

Role Summary

This senior engineering role leads verification strategy and execution for complex digital and mixed-signal IP (high-speed interfaces) used in Data Center, AI/ML, and 5G applications. The position is based in Ho Chi Minh City and requires coordinating global cross-functional teams, providing technical direction, and ensuring verification quality and schedule trade-offs.

The role involves hands-on verification architecture, methodology development, debugging, and mentoring engineers to deliver scalable verification flows.

Experience Level

Senior — expects demonstrated leadership and independent technical judgment with approximately 10+ years of experience in design verification.

Responsibilities

Lead and deliver verification for mission-critical projects; set technical direction and ensure quality and closure.

• Define and review verification strategies, test plans, coverage, assertions, and closure metrics.
• Architect and oversee robust verification environments from functional and micro-architecture specifications.
• Apply advanced verification techniques: constrained random, functional coverage, assertions, and formal verification.
• Lead complex simulation, mixed-signal and real-number modeling, RTL/GLS co-simulation, and debug efforts.
• Develop, refine, and standardize verification methodologies, frameworks, and automation for team adoption.
• Coordinate across Design, DFT, Analog, Software, Validation, and Customer teams to resolve technical and programmatic issues.
• Mentor and influence engineers at all levels; provide final technical sign-off on major verification and design decisions.
• Act as senior technical interface for customers during IP bring-up, debugging, and methodology alignment.
• Champion continuous improvement of verification flows, tools, and processes to balance quality, schedule, and scalability.

Requirements

Core technical and professional requirements; divided into must-have and nice-to-have where applicable.

• Must-have: 10+ years of experience in design verification with demonstrated leadership on complex IP projects.
• Must-have: Strong experience with VCS/Verdi simulation tools and formal verification tools (vc_formal).
• Must-have: Proven debugging skills for RTL and mixed-signal verification and experience driving coverage closure.
• Must-have: Experience defining verification strategies, architectures, and automating verification flows.
• Must-have: Strong English communication and ability to coordinate global, cross-functional teams.
• Nice-to-have: Knowledge of UVM and SystemVerilog Assertions (SVA).
• Nice-to-have: Scripting proficiency (Perl, Tcl, Python) to support automation and debug workflows.
• Nice-to-have: Experience with high-speed interface IP and customer bring-up/debug support.

Education Requirements

BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications (listed). No alternative-equivalent phrasing provided in the source.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.