Senior Staff Physical Verification CAD Engineer

Job Title

Senior Staff Physical Verification CAD Engineer

Role Summary

The Senior Staff Physical Verification CAD Engineer will develop, maintain, and support physical verification and CAD/EDA tool flows for advanced semiconductor products. The role partners with layout, design, foundry, and software teams to ensure DRC/LVS integrity, automate verification flows, and support SoC tape-out activities.

This is a senior engineering role focused on tool and methodology development, automation, validation, and cross-functional technical leadership.

Experience Level

Senior. This is a senior-level role; see Education Requirements for specific years-of-experience guidance tied to degree expectations.

Responsibilities

Primary responsibilities include developing verification flows, tool integration, and providing technical support across design and foundry interfaces.

• Develop and maintain physical verification run sets and flows for advanced process nodes; support Calibre and Synopsys ICV for DRC and LVS debugging.
• Automate and support physical verification flows, including design-rule decks and layout migration tasks.
• Support tape-out activities and coordinate with foundry engineering and SOC integration teams.
• Develop, validate, and maintain verification procedures, create validation test cases, and perform layout reviews using full-custom tools when required.
• Design, develop, and maintain CAD/EDA tools and methodologies for digital and analog IC design and physical implementation.
• Integrate third-party EDA tools into cohesive design flows and evaluate tool performance, scalability, and cost-effectiveness.
• Define and optimize design methodologies and best practices to improve productivity and reduce time-to-market.
• Provide technical guidance, user support, documentation, and training for CAD/EDA tools and workflows.
• Monitor and optimize tool performance, address issues or bottlenecks, and maintain tool reliability and stability.

Requirements

Key must-have skills and experience required for the role, followed by preferred skills.

• Must-have: Proven experience in CAD/EDA tool development and support within the semiconductor industry; hands-on experience with physical verification flows (DRC/LVS).
• Must-have: Practical experience with Synopsys ICV (required) and familiarity with industry EDA tools (Cadence, Synopsys, Mentor).
• Must-have: Proficiency in scripting for automation (Tcl, Perl, Python).
• Must-have: Strong understanding of IC design flow from RTL/synthesis to back-end physical implementation and tape-out processes.
• Must-have: Demonstrated problem-solving, leadership, and the ability to mentor and lead projects across cross-functional teams.
• Must-have: Eligibility to access export-controlled technology; candidates may be subject to export license review.
• Preferred: Experience with Mentor Calibre svrf/tvf; additional experience in SoC integration and multi-die/3DIC contexts is beneficial.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with ~5–10 years of relevant experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or related field with ~3–5 years of experience. Equivalent professional experience in lieu of a formal degree is acceptable.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.