Senior Staff Physical Design Timing Engineer (STA)

Job Title

Senior Staff Physical Design Timing Engineer (STA)

Role Summary

Responsible for STA, timing constraints development, and timing closure from synthesis through place-and-route to tapeout signoff for advanced CMOS photonics chips. Work within the backend/physical design team and collaborate with architecture, RTL, DFT, and methodology teams.

Work focuses on timing sign-off for flagship silicon photonics interconnects and improving timing flows and automation for leading-edge process nodes.

Experience Level

Senior-level. Posting indicates ~12 years of physical design experience with a minimum of 5 years hands-on ASIC STA and timing-closure experience.

Responsibilities

Primary responsibilities include timing sign-off, flow development, and cross-team coordination to achieve robust timing closure.

• Lead STA sign-off for silicon photonics chips across technology nodes.
• Develop timing constraints and modes for synthesis, PnR, and chip sign-off.
• Analyze foundry guidelines and incorporate sign-off corners, margins, and derates into timing flows.
• Run full-chip STA and project timing across scenarios and corners.
• Use Tempus/PrimeTime to automate timing ECO generation and support physical implementation.
• Evaluate tradeoffs between power, performance, and area and translate them into implementation goals.
• Document best practices and lessons learned to improve future projects.

Requirements

Must-have technical experience, tools, and working practices for this role.

• At least 12 years of physical-design experience with a minimum of 5 years hands-on in ASIC STA, timing constraints development, and timing closure using Cadence or Synopsys tools.
• Proven experience driving timing closure: managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock-tree strategies.
• Hands-on familiarity with Tempus and/or PrimeTime and automating timing ECO generation.
• Experience across synthesis through place-and-route flows and integrating timing constraints into chip execution flows.
• Scripting proficiency (TCL, Python, Perl, or Shell) for flow automation and analysis.
• Strong analytical and problem-solving skills, attention to technical detail, and clear communication.
• Ability to work with methodology teams to incorporate foundry rules and margins into timing analysis.
• Must be able to comply with U.S. export control requirements where applicable.
• Nice to have: additional senior-level hands-on ASIC STA experience (e.g., 8+ years in similar hands-on roles) or prior work on silicon photonics/mixed-signal backends.

Education Requirements

Required: Bachelor's degree in Electrical Engineering or Computer Engineering. Preferred: Master's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.