Senior Staff Physical Design Engineer
SynopsysJob Title
Senior Staff Physical Design Engineer
Role Summary
Senior individual contributor responsible for driving timing closure, signoff readiness, and physical implementation methodologies for advanced-node ASIC designs. Works across block, subsystem, and full-chip teams to deliver production silicon on aggressive process nodes.
Experience Level
Senior-level. The role expects approximately 8+ years of hands-on ASIC physical design, implementation, and timing-closure experience.
Responsibilities
Deliver technical leadership and hands-on implementation support across advanced-node physical-design projects.
- Drive timing closure and signoff readiness for advanced nodes (5nm, 3nm, and below) at block, subsystem, and full-chip levels.
- Develop and refine physical-design methodologies and automation flows using TCL, Python, and Perl.
- Perform static timing analysis, clock-tree synthesis, and ECO implementation using industry implementation and signoff tools.
- Analyze PPA and design data to identify bottlenecks and improve workflows and predictability.
- Collaborate with front-end design, verification, and CAD teams to ensure on-schedule silicon delivery.
- Troubleshoot congestion, power-integrity, and multi-corner timing convergence; create scalable, reusable solutions.
- Contribute to AI/ML-assisted design optimization and data-driven engineering initiatives.
Requirements
Key technical requirements and desired experience. Items labeled "Nice-to-have" are not mandatory.
- Must-have: 8+ years of hands-on ASIC physical design and timing-closure experience at block, subsystem, or chip level.
- Must-have: Deep expertise with implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus.
- Must-have: Strong working knowledge of timing, power, and signoff tools (e.g., PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, Conformal).
- Must-have: Proven ability to build flows, methodologies, and automation using TCL, Python, Perl, or similar scripting languages.
- Must-have: Experience with advanced-node semiconductor design at 7nm or below and associated implementation challenges.
- Nice-to-have: Exposure to machine learning or AI-assisted design optimization and data-driven workflows.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
