Senior Staff Physical Design Engineer
QualcommJob Title
Senior Staff Physical Design Engineer
Role Summary
Lead physical implementation (PNR) for Qualcomm SoC projects, focusing on floorplanning, placement, clock tree synthesis, post-route optimization and signoff. Member of the ASICS Engineering team collaborating with timing, power, verification and integration groups to deliver high-performance, low-power designs on advanced process nodes.
Experience Level
Senior-level. The posting emphasizes extensive PNR and hardware-engineering experience (typically 12+ years is preferred); alternate minimum pathways are listed: Bachelor's +6 years, Master's +5 years, PhD +4 years.
Responsibilities
Primary responsibilities for this role include ownership of physical implementation and signoff on advanced-node SoCs.
- Own full PNR implementation: floorplanning, placement, CTS, routing, and post-route optimization.
- Perform static timing analysis (STA) signoff and power signoff; resolve timing and power closure issues.
- Coordinate low-power verification, formal verification (FV) and other signoff flows as required.
- Work cross-functionally with RTL, synthesis, timing, power, verification, and PDN teams to meet product goals.
- Develop and maintain Unix/Linux-based scripts and automation (Perl/Tcl or similar) to support flow efficiency.
- Analyze and optimize placement/CTS and implementation to meet performance, power and area targets.
Requirements
Key technical requirements and experience (must-have vs nice-to-have):
- Must-have: Proven ownership of PNR/physical implementation flows on SoC projects.
- Must-have: Strong signoff experience (STA, power analysis) and familiarity with signoff verification flows.
- Must-have: Hands-on experience with placement, CTS, optimization and post-route tasks on advanced nodes (4nm/5nm/7nm/10nm).
- Must-have: Proficiency with Unix/Linux and scripting (Perl, Tcl, or equivalent) to automate flows.
- Must-have: Strong analytical, debugging and problem-solving skills; ability to drive closure on timing and power issues.
- Nice-to-have: Experience with signoff domains and tools such as LEC/CLP/PDN analyses, low-power verification and formal verification integration.
- Nice-to-have: Experience specifically with 12+ years in hardware engineering or extended PNR experience on the latest process nodes.
Education Requirements
The posting references degree-based and experience-based pathways: Bachelor's, Master's or PhD in Science, Engineering, or a related field. Minimums tied to degrees are listed as: Bachelor's +6 years, Master's +5 years, PhD +4 years. The posting also notes alternative experience expectations (e.g., listings for 12+ years of hardware/PNR experience).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
