Senior/Staff NAND Design Rule Engineer

Job Title

Senior/Staff NAND Design Rule Engineer

Role Summary

As a Senior/Staff NAND Design Rule Engineer in Process Integration (Storage Technology Group), you will define and implement physical design rules and mask/layout generation for next-generation 3D NAND technologies. The role coordinates across process, design, verification, and mask teams to enable timely technology development and production ramp.

Experience Level

Senior level. Candidate should have at least 3 years of semiconductor industry experience (per the posted qualification) and demonstrated domain expertise.

Responsibilities

Primary responsibilities include technical definition, verification, and automation of design rules and mask/data generation.

• Define physical design rules for current and future NVM technologies from concept through production ramp.
• Work with process integration teams to keep design rules aligned with technology developments.
• Evaluate layout and architecture options with design teams to identify rule and process limitations.
• Develop automation and agentic tools to ensure comprehensive, accurate, and consistent design-rule coverage.
• Support design-rule checking (DRC) for base and mask layers and coordinate with physical verification teams.
• Define algorithms and workflows for generating mask data from drawn base-layer data.
• Investigate product and test-structure failures and their interaction with layout and mask data.
• Collaborate across multidisciplinary project teams to resolve layout and mask-generation issues.

Requirements

Must-have technical skills and experience:

• Strong knowledge of semiconductor device physics, VLSI silicon processing, and integration flows.
• Proven ability to develop code and automation using Python or similar programming languages and tools.
• Experience with CAD/layout tools such as Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE; familiarity with physical verification workflows.
• Experience with design-rule checking, mask-layer handling, and data post-processing for reticle transfer.
• Understanding of memory scaling challenges and key NAND components (BL sensing, word-line driver, CMOS under array).
• Strong written, verbal, and presentation communication skills.

Nice-to-have:

• Familiarity with Claudecode or similar industry tools.
• Experience developing algorithms for mask-data generation and advanced automation/agentic solutions.

Education Requirements

Master’s or PhD degree required; the posting specifies a Master’s or PhD with at least 3 years of semiconductor industry experience in areas such as Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.