Senior Staff Manager, Subsystem CoE - Emulation

Job Title

Senior Staff Manager, Subsystem CoE - Emulation

Role Summary

Lead the Emulation Center of Excellence (CoE) in Bangalore to deliver scalable SoC emulation infrastructure, enable pre-silicon validation, and drive software readiness and post-silicon success across key subsystems (boot, security, PCIe, CXL, DDR/HBM, Ethernet, USB, and peripherals).

Manage development of emulation models and environments, coordinate with RTL/verification/firmware teams, and define emulation strategy and execution across commercial emulation platforms.

Experience Level

Senior-level. The role expects extensive experience — typically 12+ years of hands-on digital design, emulation, validation, and debug.

Responsibilities

Primary responsibilities include building and operating emulation infrastructure, driving bring-up and validation activities, and enabling cross-functional teams.

• Lead development of complex SoC emulation models and environment setup on platforms such as Veloce, ZeBu, and Palladium.
• Drive emulation bring-up: clock/reset sequencing, firmware boot, and system validation using pre-silicon hardware models.
• Create and execute emulation test plans to support verification, performance analysis, software development, and system validation.
• Collaborate with RTL design, verification, and firmware teams to define requirements and ensure integration into the emulation environment.
• Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchains.
• Optimize emulation performance through model partitioning, timing adjustments, and runtime efficiency improvements.
• Automate flows and improve productivity using scripting and tooling enhancements.
• Interface with EDA vendors to evaluate tools, resolve technical issues, and drive feature improvements.
• Define and execute emulation strategy across multiple subsystems and enable firmware/software teams with stable, scalable environments.

Requirements

Must-have skills and experience:

• 12+ years of hands-on digital design experience, including use of EDA tools for logic synthesis, timing analysis, and formal verification.
• Strong experience in SoC emulation, pre-silicon validation, and system-level debug.
• Hands-on experience with emulation platforms: Palladium, ZeBu, Veloce.
• Deep understanding of SoC architecture, interconnects, and system integration.
• Expertise in one or more domains: boot flow/system initialization, security validation, PCIe/CXL/Ethernet, DDR/HBM, SPI/I2C/UART, USB 3.0.
• Proficiency in scripting and automation: Python, Perl, Tcl, Shell.
• Strong debugging skills across the HW/SW boundary and proven ability to lead cross-functional efforts.

Nice-to-have:

• Experience working with EDA vendors (Synopsys, Cadence, Siemens) and influencing tool capabilities.
• Experience in performance analysis, model partitioning, and runtime optimization.

Education Requirements

Master's degree in Electronics/Electrical Engineering or a related field with coursework in digital circuit design (as stated in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.