Senior Staff Manager

Job Title

Senior Staff Manager

Role Summary

Lead verification and subsystem design teams for complex SoCs, responsible for verification strategy, testbench development, and coordination with architecture, RTL, DFT, PD, and customer teams. Manage delivery of subsystem IPs from DV sign-off through integration and production ramp.

Drive automation and adoption of AI tools to improve verification and design flows while aligning engineering roadmaps with business objectives.

Experience Level

Senior — 15–18+ years in VLSI design with at least 3–5 years in formal management or technical lead roles.

Responsibilities

The role combines technical leadership in design verification with people and project management.

• Lead UVM/SystemVerilog testbench development and constrained-random verification for subsystems using third-party VIPs.
• Define and own DV strategy, verification specification (MAS), and subsystem test plans; drive coverage closure and DV sign-off.
• Coordinate reviews and interfaces with Architecture, RTL, DFT, PD, and customer teams.
• Manage and mentor teams of design and DV engineers; provide technical guidance across RTL coding, synthesis, lint, CDC, and LEC.
• Integrate and customize third-party IP/VIP into subsystems.
• Drive automation and scripting (Perl, Python, Tcl) and adopt AI tools to improve verification and design flows.
• Work with interconnect fabrics and protocols (ARM/Arteris fabrics, AXI/APB, NoC).
• Report status and align engineering roadmaps with business objectives and executive leadership.
• Ensure compliance with export-control requirements where applicable.

Requirements

Must-have technical skills and experience.

• 15–18+ years hands-on VLSI experience; 3–5 years in management or technical lead capacity.
• Strong expertise in Verilog, SystemVerilog and UVM; unit and subsystem verification experience.
• Proficiency in SystemVerilog, C/C++, and scripting (Perl, Tcl, Python).
• Experience integrating third-party IP/VIP and knowledge of peripheral IPs (QSPI, SPI, I3C, I2C, PMBus, AVSBus, GPIO, DMA, Fuse Controller, UART).
• Experience with interconnect fabrics/protocols (ARM/Arteris, AXI/APB, NoC) and verification flow optimization and debugging.
• Excellent verbal and written communication skills and ability to align technical work with business objectives.
• Strong inclination to use AI tools for automation.

Education Requirements

Not specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.