Senior Staff Manager, DDR/HBM

Job Title

Senior Staff Manager, DDR/HBM

Role Summary

Lead a technical team within Marvell Data Centre Engineering (Compute & Storage BU) responsible for memory subsystem architecture, RTL implementation, integration, and validation for complex SoCs. The role combines people leadership, cross‑functional coordination, and hands‑on architectural oversight for DDR/HBM memory subsystems.

Primary mission: deliver high‑quality, high‑performance memory subsystems integrated into large chips and platforms, and to grow team capability through mentorship and process improvements.

Experience Level

Senior — requires extensive industry experience; the posting specifies 18+ years of relevant industry experience including technical leadership and people management.

Responsibilities

Key responsibilities include leading architecture and implementation of memory subsystems and managing team delivery.

• Provide technical mentorship and people leadership; grow team capability and coach junior engineers.
• Define memory subsystem architecture, micro‑architecture, and register specifications for complex SoCs.
• Drive and review specifications to align architecture, design, verification, and software teams.
• Lead architectural, performance, and design reviews with cross‑functional stakeholders, IP vendors, and customers.
• Guide and review RTL implementation to ensure coding standards, design quality, and architectural intent.
• Coordinate with third‑party IP vendors to define customization and integration requirements for controllers, PHYs, and related IP.
• Partner with physical design teams on floorplanning, power analysis, synthesis, and timing signoff.
• Collaborate with verification teams on pre‑silicon activities: test plans, coverage analysis, full‑chip simulation/emulation, performance analysis, and debug.
• Drive continuous improvement of design and verification methodologies, tools, and execution models.
• Support post‑silicon validation and software teams during prototype bring‑up, debug, and performance tuning.
• Own resource planning, task prioritization, execution tracking, and delivery commitments for the team.

Requirements

Must‑have technical skills and experience for successful performance in this role.

• Extensive experience in technical leadership and people management of engineering teams.
• Proven track record leading architecture, micro‑architecture, and register specification development for complex SoCs.
• Strong Verilog/SystemVerilog RTL design expertise, including SystemVerilog assertions and best coding practices.
• Deep understanding of the full ASIC development lifecycle: specification, architecture, RTL implementation, integration, and prototype bring‑up.
• Expertise in high‑speed memory subsystems and protocols (DDR4/DDR5, LPDDR4/LPDDR5X, HBM3).
• Experience owning and delivering complex chips or large subsystems (network processors, CPUs, GPUs, NoCs, switches, or ML SoCs).
• Demonstrated experience managing and reviewing full‑chip, subsystem, and block‑level architecture and design verification.
• Proficiency in scripting for automation (Perl, Python, Shell).
• Strong communication skills with experience interfacing across cross‑functional teams, IP vendors, and customers.
• Nice to have: domain expertise in networking, embedded systems architecture, computer architecture, or machine learning accelerators.

Education Requirements

Master's or Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field (as stated in the posting). The role also specifies 18+ years of relevant industry experience and expects demonstrated technical leadership; no specific certifications were listed.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.