Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe/CXL/DDR/Ethernet)
SynopsysJob Title
Senior Staff Interface IP Verification Engineer (Pre-Silicon - PCIe/CXL/DDR/Ethernet)
Role Summary
Lead the pre-silicon verification of high-speed Interface IP (PCIe, CXL, DDR, Ethernet) from architecture review through silicon signoff. Build and maintain reusable UVM-based verification environments and define verification strategies that ensure protocol compliance and system-level reliability.
The role requires technical leadership across architecture, design, firmware, and systems teams and mentorship of verification engineers to raise verification quality across product generations.
Experience Level
Senior - requires 8+ years of hands-on ASIC or SoC verification experience.
Responsibilities
Primary responsibilities include ownership of verification strategy, environment development, debugging, and cross-team collaboration.
- Own end-to-end verification of Interface IP blocks (PCIe, CXL, DDR, Ethernet) through silicon signoff.
- Design, build, and evolve scalable, reusable UVM-based verification environments.
- Define verification strategies and test plans for protocol compliance, performance corner cases, and system integration scenarios.
- Develop constrained-random, coverage-driven test scenarios targeting functional coverage closure and signoff quality.
- Debug multi-layer issues across RTL logic, protocol state machines, timing, and testbench infrastructure using industry simulators.
- Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early.
- Mentor and coach verification engineers on methodology, coverage analysis, and debugging best practices.
Requirements
Must-have technical skills and practical verification experience; listed plus items are desirable.
- Deep expertise in SystemVerilog and UVM methodology; track record building scalable verification environments.
- Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet and ability to translate specs into verification requirements.
- Proven experience with constrained-random and coverage-driven verification achieving functional signoff.
- Strong debugging skills across RTL, verification infrastructure, and protocol compliance; experience with simulators such as VCS or ModelSim (or equivalents).
- Experience developing verification IP and using assertion-based verification.
- Experience leading verification efforts and mentoring engineers; effective cross-team communication with architects and design leads.
- Nice-to-have: formal methods experience and knowledge of modern SoC architectures and high-speed communication interfaces.
Education Requirements
Requires a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. The posting specifies 8+ years of hands-on ASIC/SoC verification experience alongside the degree requirement.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
