Senior/Staff IC Packaging Engineer — Mechanical Simulation

Job Title

Senior/Staff IC Packaging Engineer — Mechanical Simulation

Role Summary

Member of the IC package engineering process team providing mechanical Finite Element Analysis (FEA) support for high-volume manufacturing and advanced packaging technologies. The role works with design, NPI and Chip-Package Interaction (CPI) teams to develop FEA models, improve simulation workflows, and correlate predictions with test data.

Primary focus areas include warpage and stress analysis, solder joint reliability prediction, package assembly process simulation, and CPI/board-level interaction analyses to support package design and reliability.

Experience Level

Senior level. Preferred experience indicated: typically 3+ years in mechanical FEA for semiconductor/IC packaging; preferred candidates may have 5+ years or staff-level experience.

Responsibilities

Key responsibilities include development, validation and application of mechanical simulation methods for IC packages.

• Develop and maintain mechanical FEA models and APDL/workbench workflows for IC packages.
• Establish FEA methodologies and best-known-methods (BKMs) and maintain macros/workflows to improve prediction accuracy and throughput.
• Perform warpage, stress and solder joint reliability analyses; perform contact and non-linear analyses and sub-modeling as needed.
• Simulate package assembly and process flows to predict failures and support design-for-reliability decisions.
• Support material characterization and test correlation to refine simulation models.
• Collaborate with design, NPI, CPI and manufacturing teams and present results to stakeholders.
• Drive project execution, documentation of methods, and continuous improvement of simulation workflows.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 3+ years of mechanical FEA experience focused on semiconductor / IC microelectronic packaging industries (minimum requirement indicated).
• 2+ years hands-on experience with ANSYS (APDL and Workbench).
• Practical knowledge of FEA techniques: sub-modeling, contact analysis, non-linear analysis, and model correlation to test.
• Experience with warpage/stress analysis, solder joint reliability prediction, package assembly/process simulation, and CPI/board interaction analysis.
• Experience in material characterization/testing and developing methods to improve model accuracy.
• Strong analytical, communication and project execution skills; ability to work across time zones and with cross-functional teams.
• Willingness to travel occasionally for domestic and international collaboration.

Preferred:

• 5+ years combined experience in FEA for IC packaging and interconnects; research/publications in warpage, CPI or solder lifetime prediction considered a plus.
• Experience developing predictive BKMs and improving simulation workflows to support manufacturing and reliability.
• Familiarity with using AI tools to accelerate APDL coding and simulation automation (plus).

Education Requirements

Degrees mentioned in the source: Bachelor's, Master's and PhD in Mechanical Engineering, Materials Science, Electrical/Microelectronics Engineering, Chemical Engineering or related engineering fields. The posting also allows equivalent practical experience in place of formal degrees (degree/experience equivalencies provided for Bachelor's/Master's/PhD levels).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.