Senior Staff IC/FPGA Design Verification Engineer

Job Title

Senior Staff IC/FPGA Design Verification Engineer

Role Summary

Lead verification for high-speed interconnect IP, subsystems, and related FPGA prototypes. Provide technical leadership across IP, subsystem, and system-level verification and collaborate with architecture, design, software, validation, and customer teams to deliver production-quality ASICs and FPGAs.

Experience Level

Senior-level. The posting cites degree-based minimums (Bachelor's +6 years; Master's +5 years; PhD +4 years) and additional guidance elsewhere (MSc/MEng with 7+ years or BSc/BEng with 10+ years) for ASIC/FPGA development and verification experience.

Responsibilities

Primary responsibilities include verification leadership, environment development, and cross-team collaboration.

• Deliver standards-compliant IP blocks and subsystems for PCIe, CXL, UALink, Ethernet, and next-generation interconnects.
• Provide technical leadership for verification across IP, subsystem, and system levels.
• Architect, develop, and document scalable verification environments using SystemVerilog and UVM.
• Develop comprehensive verification test plans and drive verification closure.
• Create, debug, and optimize complex test cases to meet functional and coverage goals.
• Drive bug tracking, root-cause analysis, and resolution from discovery through closure.
• Improve engineering productivity through tools, automation, and AI-driven verification techniques.
• Mentor engineers and promote verification best practices across teams.

Requirements

Must-have technical skills and experience. Education and specific degree-year combinations are summarized separately under Education Requirements.

• Deep knowledge of high-speed communication and interconnect protocols (PCIe, CXL, UALink, Ethernet).
• Expert-level experience with SystemVerilog, UVM, constrained-random techniques, and coverage-driven verification.
• Strong understanding of IP, subsystem, and SoC-level verification methodologies.
• Extensive experience with simulation, debugging, verification closure, functional coverage, and assertion-based verification.
• Proven technical leadership, strong communication, and problem-solving skills; ability to influence cross-functional teams.

Nice-to-have:

• Experience with PCIe Gen5/6/7 or CXL 3.0/4.0 across Physical through Transaction layers.
• Experience with UALink and AI/HPC interconnect technologies.
• Familiarity with PCIe/CXL VIPs from Siemens/Avery, Cadence, or Synopsys.
• Experience leveraging AI-based approaches for test generation, debug, and coverage closure.
• Experience with formal verification, emulation, or FPGA prototyping and defining cross-project verification methodologies.

Education Requirements

Posting references degrees in Science or Engineering (e.g., BSc/BEng, MSc/MEng, PhD) or related fields. Degree-plus-experience combinations cited: Bachelor's degree with ~6+ years, Master's degree with ~5+ years, PhD with ~4+ years (per Minimum Qualifications); another section references MSc/MEng with 7+ years or BSc/BEng with 10+ years. Equivalent practical experience is presented as alternative paths in the posting.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.