Senior Staff High-Speed Interface Verification Engineer

Job Title

Senior Staff High-Speed Interface Verification Engineer

Role Summary

Lead verification of high-speed SerDes and other high-speed interface IP using UVM/SystemVerilog in mixed-signal co-simulation environments. Work closely with digital, analog, and mixed-signal design teams to define verification strategy from architecture through tapeout and to support customer escalations and product adoption.

Experience Level

Senior - requires 7+ years of hands-on verification experience in ASIC or mixed-signal environments.

Responsibilities

Accountable for technical verification delivery, cross-domain debug, and customer-facing technical activities.

• Lead verification of SerDes and high-speed interfaces using UVM/SystemVerilog in mixed-signal co-simulation flows.
• Define, track, and execute verification plans for PCIe, Ethernet, USB3.1 and similar protocols from architecture to tapeout.
• Build and extend UVM testbenches: constrained-random sequences, coverage models, checkers, sequence libraries, scoreboards, and monitors.
• Debug simulation failures across digital and analog domains using waveform viewers, AMS simulators, and protocol analyzers.
• Collaborate with design teams to align verification with design intent and silicon bring-up requirements.
• Manage customer escalations: reproduce issues, isolate root cause, and drive resolution with engineering and field teams.
• Participate in pre-sales and post-sales technical discussions to translate verification results into customer confidence.
• Mentor peers, establish best practices, and perform code reviews to improve team capability and quality.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Deep expertise in UVM, SystemVerilog, constrained-random testing, functional coverage, and assertions.
• Proven experience with digital/analog co-simulation tools and mixed-signal verification flows (AMS simulators).
• Working knowledge of high-speed protocols (PCIe, Ethernet, USB3.1) and protocol-level verification/compliance.
• Strong understanding of full ASIC development flow: architecture, RTL verification, and hardware bring-up.
• Experienced in writing complex system-level UVM testbenches including sequence libraries, scoreboards, and protocol monitors.
• Hands-on ability to debug waveform-level failures in both digital logic and analog circuit behavior.
• Proven ability to manage customer escalations and communicate technical status to engineering and field teams.

Education Requirements

MTech or BTech in Electronics, Electrical Engineering, Computer Science, or equivalent; or equivalent practical experience. (The source specifies 7+ years of relevant verification experience.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.