Senior Staff High-Speed I/O Design Engineer

Job Title

Senior Staff High-Speed I/O Design Engineer

Role Summary

Design analog and mixed-signal PHY circuits for UCIe and high-speed die-to-die interfaces, focusing on transmitters, receivers, equalization, clocking, and calibration to meet BER, jitter, power, and area targets.

Work with cross-functional teams (digital, layout, signal integrity, packaging, validation) from architecture through silicon bring-up and lab characterization to ensure first-pass silicon success.

Experience Level

Senior - typically 8 to 15 years of hands-on analog or mixed-signal IC design experience focused on high-speed interfaces.

Responsibilities

Lead circuit architecture, design, verification, and silicon bring-up for high-speed I/O PHY IP.

• Define analog PHY architectures and translate system requirements into circuit-level specs for TX, RX, equalization, clocking, and calibration.
• Design transistor-level circuits (TX drivers, RX front-ends, CTLE, DFE, DLLs, bias/termination) and perform schematic-level simulation.
• Build behavioral models for link performance, jitter budgeting, and BER estimation to guide system trade-offs.
• Verify designs across PVT corners, Monte Carlo, aging, reliability, and post-layout parasitics; ensure design margin before tapeout.
• Analyze package, interposer, substrate, and channel effects; collaborate with SI and packaging engineers on channel impact.
• Support floor planning, layout reviews, parasitic back-annotation, and sign-off to meet area, power, and performance targets.
• Lead silicon bring-up, lab characterization, compliance testing, and simulation-to-silicon correlation; drive root-cause analysis and fixes.
• Mentor junior engineers and contribute to design documentation and IP release processes.

Requirements

Must-have technical skills and experience.

• Extensive analog/mixed-signal IC design experience focused on high-speed I/O (UCIe, die-to-die interconnects, SerDes, PCIe, Ethernet, CXL, USB, or similar).
• Deep expertise in transmitter and receiver design, equalization, DLLs, bias circuits, jitter and phase-noise analysis, and signal-integrity trade-offs.
• Proficiency with transistor-level design and simulation tools such as Cadence Virtuoso/Spectre or Synopsys Custom Compiler/HSPICE.
• Experience with schematic design, behavioral modeling, parasitic extraction, post-layout verification, and sign-off in advanced process nodes.
• Hands-on silicon bring-up and lab measurement experience using high-speed scopes and BERTs; able to correlate lab results to simulation.
• Ability to work with layout and SI engineers during floor planning to manage parasitics, coupling, and return paths.
• Strong communication skills to explain analog trade-offs to digital teams and lead cross-functional debugging.
• Nice-to-have: familiarity with compliance testing, industry standards, and experience mentoring or leading small teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field, or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.