Senior Staff Engineer, SystemVerilog & Digital Verification
XoriantJob Title
Senior Staff Engineer, SystemVerilog & Digital Verification
Role Summary
Member of a large RFC/RFIC/DFT engineering organization responsible for advanced digital verification of complex SoC and mixed-signal designs. The role focuses on block-level and full-chip verification using UVM and SystemVerilog.
Works closely with RTL designers and system architects to define verification strategy, build environments, execute regressions, and perform deep RTL and protocol-level debugging. On-site in San Jose, CA.
Experience Level
Senior — approximately 15+ years of hands-on digital verification experience preferred.
Responsibilities
The core responsibilities include designing and executing verification plans, building UVM environments, and debugging complex RTL and protocol issues.
- Define verification strategy for blocks and full-chip integration in collaboration with architects and RTL designers.
- Design and implement UVM environments from scratch using SystemVerilog.
- Develop constrained-random and directed tests; implement functional coverage models and analyze coverage closure.
- Manage regressions, maintain testbenches, and run large-scale regression suites.
- Perform deep RTL and protocol-level debugging across interfaces and subsystems.
- Support low-power verification flow using UPF and related methodologies.
- Use Cadence-based EDA tools; work with VCS/Questa and formal verification tools as applicable.
- Integrate verification with mixed-signal/DMS and subsystem-level validation where required.
Requirements
Must-have technical skills and experience for effective performance in this role.
- 15+ years hands-on digital verification experience (practical, execution-driven).
- Expertise in SystemVerilog and UVM for verification environment development.
- Strong knowledge of AMBA protocols (AXI, AHB, APB) and common interfaces (SPI, UART, JTAG, TileLink, custom interconnects).
- Solid CPU/SoC fundamentals: processor architectures, cache coherency, and memory hierarchy.
- Proven RTL and protocol debugging skills and strong problem-solving mindset.
- Experience with Cadence EDA tools; familiarity with VCS/Questa and formal tools is a plus.
- Ability to work on-site in San Jose, CA and collaborate closely with cross-functional teams.
- Execution-focused, able to build environments and deliver verification results quickly.
Education Requirements
Not specified.
About the Company
Company: Xoriant
Headquarters: Sunnyvale, CA, USA
Product engineering and technology services firm providing software and embedded systems engineering, product development, cloud and digital transformation services for ISVs and enterprises.
