Senior Staff Engineer, RTL ASIC Design

Job Title

Senior Staff Engineer, RTL ASIC Design

Role Summary

Lead subsystem architecture, specification and RTL implementation for complex SoC designs within the Custom and Compute Solutions Business Unit. Work across architecture, verification, IP integration and system teams to define roadmaps, KPIs, and delivery of subsystem collateral.

This role focuses on driving technical trade-offs for performance, power, security and scalability, coordinating with third-party IP vendors, and mentoring junior engineers.

Experience Level

Senior. Typical experience: Bachelor's degree plus 8+ years professional experience, or Master's/PhD with ~6+ years of experience.

Responsibilities

Primary responsibilities include subsystem ownership, cross-team coordination, and delivery of design collateral.

• Own roadmap and execution of a subsystem; make architectural and standards decisions.
• Define and track KPIs for performance, power, security, scalability and compliance; make technical trade-offs to meet targets.
• Specify and deliver architecture specs, PRDs, integration guides, reference designs, performance models and benchmarks.
• Collaborate with third-party IP vendors to define customization, requirements and IP roadmaps.
• Drive verification strategy at the subsystem level and coordinate with verification teams on test plans, full-chip simulation/emulation, and debug.
• Work closely with SoC chief engineers, product architecture, PD, DFT, firmware/software and system teams during design and bring-up.
• Mentor and guide junior engineers on architecture and implementation choices.

Requirements

Technical skills and experience required to perform the role. Degree details are in the Education Requirements section below.

• Must-have: Strong Verilog/SystemVerilog RTL coding skills and experience with SystemVerilog assertions (SVA).
• Hands-on experience across ASIC design flow stages: specification, architecture, design implementation and prototype bring-up.
• Experience owning subsystem and block-level architecture on complex chips (network processors, CPUs, GPUs, NOCs, switches, ML SoCs).
• Experience with peripheral interface IPs and protocols (I3C, I2C, SPI/QSPI, UART, GPIO, USB).
• Experience integrating third-party IP from vendors (Synopsys, Cadence, ARM) and customizing IP for subsystem integration.
• Experience with interconnect fabrics and protocols (AMBA/AXI/APB, Arm/Arteris fabrics, NoC architectures).
• Scripting experience in Perl/Python/Shell; practical use of AI tools and agents for engineering tasks.
• Ability to lead collaboration with verification, performance/power analysis and system teams.
• Eligible to access export-controlled technology where required; may be subject to export license review.
• Nice-to-have: Prior work with machine-learning SoCs, performance modeling and benchmarking, and deep experience with specific vendor IP customization.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or a related field (required) with 8+ years of related professional experience. Alternatively, a Master's degree or PhD in Computer Science, Electrical Engineering or related fields with 6+ years of professional experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.